Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull KVM updates from Paolo Bonzini: "Small release, the most interesting stuff is x86 nested virt improvements. x86: - userspace can now hide nested VMX features from guests - nested VMX can now run Hyper-V in a guest - support for AVX512_4VNNIW and AVX512_FMAPS in KVM - infrastructure support for virtual Intel GPUs. PPC: - support for KVM guests on POWER9 - improved support for interrupt polling - optimizations and cleanups. s390: - two small optimizations, more stuff is in flight and will be in 4.11. ARM: - support for the GICv3 ITS on 32bit platforms" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (94 commits) arm64: KVM: pmu: Reset PMSELR_EL0.SEL to a sane value before entering the guest KVM: arm/arm64: timer: Check for properly initialized timer on init KVM: arm/arm64: vgic-v2: Limit ITARGETSR bits to number of VCPUs KVM: x86: Handle the kthread worker using the new API KVM: nVMX: invvpid handling improvements KVM: nVMX: check host CR3 on vmentry and vmexit KVM: nVMX: introduce nested_vmx_load_cr3 and call it on vmentry KVM: nVMX: propagate errors from prepare_vmcs02 KVM: nVMX: fix CR3 load if L2 uses PAE paging and EPT KVM: nVMX: load GUEST_EFER after GUEST_CR0 during emulated VM-entry KVM: nVMX: generate MSR_IA32_CR{0,4}_FIXED1 from guest CPUID KVM: nVMX: fix checks on CR{0,4} during virtual VMX operation KVM: nVMX: support restore of VMX capability MSRs KVM: nVMX: generate non-true VMX MSRs based on true versions KVM: x86: Do not clear RFLAGS.TF when a singlestep trap occurs. KVM: x86: Add kvm_skip_emulated_instruction and use it. KVM: VMX: Move skip_emulated_instruction out of nested_vmx_check_vmcs12 KVM: VMX: Reorder some skip_emulated_instruction calls KVM: x86: Add a return value to kvm_emulate_cpuid KVM: PPC: Book3S: Move prototypes for KVM functions into kvm_ppc.h ...
这个提交包含在:
@@ -304,8 +304,11 @@ OPAL_CALL(opal_pci_get_presence_state, OPAL_PCI_GET_PRESENCE_STATE);
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OPAL_CALL(opal_pci_get_power_state, OPAL_PCI_GET_POWER_STATE);
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OPAL_CALL(opal_pci_set_power_state, OPAL_PCI_SET_POWER_STATE);
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OPAL_CALL(opal_int_get_xirr, OPAL_INT_GET_XIRR);
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OPAL_CALL_REAL(opal_rm_int_get_xirr, OPAL_INT_GET_XIRR);
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OPAL_CALL(opal_int_set_cppr, OPAL_INT_SET_CPPR);
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OPAL_CALL(opal_int_eoi, OPAL_INT_EOI);
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OPAL_CALL_REAL(opal_rm_int_eoi, OPAL_INT_EOI);
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OPAL_CALL(opal_int_set_mfrr, OPAL_INT_SET_MFRR);
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OPAL_CALL_REAL(opal_rm_int_set_mfrr, OPAL_INT_SET_MFRR);
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OPAL_CALL(opal_pci_tce_kill, OPAL_PCI_TCE_KILL);
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OPAL_CALL_REAL(opal_rm_pci_tce_kill, OPAL_PCI_TCE_KILL);
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@@ -896,3 +896,5 @@ EXPORT_SYMBOL_GPL(opal_leds_get_ind);
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EXPORT_SYMBOL_GPL(opal_leds_set_ind);
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/* Export this symbol for PowerNV Operator Panel class driver */
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EXPORT_SYMBOL_GPL(opal_write_oppanel_async);
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/* Export this for KVM */
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EXPORT_SYMBOL_GPL(opal_int_set_mfrr);
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@@ -63,7 +63,7 @@ static long ps3_hpte_insert(unsigned long hpte_group, unsigned long vpn,
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vflags &= ~HPTE_V_SECONDARY;
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hpte_v = hpte_encode_v(vpn, psize, apsize, ssize) | vflags | HPTE_V_VALID;
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hpte_r = hpte_encode_r(ps3_mm_phys_to_lpar(pa), psize, apsize, ssize) | rflags;
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hpte_r = hpte_encode_r(ps3_mm_phys_to_lpar(pa), psize, apsize) | rflags;
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spin_lock_irqsave(&ps3_htab_lock, flags);
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@@ -145,7 +145,7 @@ static long pSeries_lpar_hpte_insert(unsigned long hpte_group,
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hpte_group, vpn, pa, rflags, vflags, psize);
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hpte_v = hpte_encode_v(vpn, psize, apsize, ssize) | vflags | HPTE_V_VALID;
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hpte_r = hpte_encode_r(pa, psize, apsize, ssize) | rflags;
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hpte_r = hpte_encode_r(pa, psize, apsize) | rflags;
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if (!(vflags & HPTE_V_BOLTED))
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pr_devel(" hpte_v=%016lx, hpte_r=%016lx\n", hpte_v, hpte_r);
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