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tg3: Enable support for timesync gpio output

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The PTP_CAPABLE tg3 devices have a gpio output that is toggled when the
free running counter matches a watchdog value. This patch adds support
to set the watchdog and enable this feature.

Since the output is controlled via bits in the EAV_REF_CLCK_CTL
register, we have to read-modify-write it when we stop/resume.

Cc: Richard Cochran <richardcochran@gmail.com>
Signed-off-by: Nithin Nayak Sujir <nsujir@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Nithin Sujir
2013-07-29 13:58:38 -07:00
committed by David S. Miller
parent 4c305fa2cb
commit 92e6457d4c
2 changed files with 68 additions and 4 deletions
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11
drivers/net/ethernet/broadcom/tg3.h
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@@ -1818,12 +1818,21 @@
#define TG3_EAV_REF_CLCK_CTL 0x00006908
#define TG3_EAV_REF_CLCK_CTL_STOP 0x00000002
#define TG3_EAV_REF_CLCK_CTL_RESUME 0x00000004
#define TG3_EAV_CTL_TSYNC_GPIO_MASK (0x3 << 16)
#define TG3_EAV_CTL_TSYNC_WDOG0 (1 << 17)
#define TG3_EAV_WATCHDOG0_LSB 0x00006918
#define TG3_EAV_WATCHDOG0_MSB 0x0000691c
#define TG3_EAV_WATCHDOG0_EN (1 << 31)
#define TG3_EAV_WATCHDOG_MSB_MASK 0x7fffffff
#define TG3_EAV_REF_CLK_CORRECT_CTL 0x00006928
#define TG3_EAV_REF_CLK_CORRECT_EN (1 << 31)
#define TG3_EAV_REF_CLK_CORRECT_NEG (1 << 30)
#define TG3_EAV_REF_CLK_CORRECT_MASK 0xffffff
/* 0x690c --> 0x7000 unused */
/* 0x692c --> 0x7000 unused */
/* NVRAM Control registers */
#define NVRAM_CMD 0x00007000