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net/mlx5e: Wake On LAN support

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Implement set/get WOL by ethtool and added the needed
device commands and structures to mlx5_ifc.

Signed-off-by: Tariq Toukan <tariqt@mellanox.com>
Signed-off-by: Rana Shahout <ranas@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Tariq Toukan
2016-02-22 18:17:29 +02:00
committed by David S. Miller
parent d8880795da
commit 928cfe8745
6 changed files with 243 additions and 1 deletions
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11
include/linux/mlx5/device.h
View File

@@ -1183,6 +1183,17 @@ enum {
MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
};
enum mlx5_wol_mode {
MLX5_WOL_DISABLE = 0,
MLX5_WOL_SECURED_MAGIC = 1 << 1,
MLX5_WOL_MAGIC = 1 << 2,
MLX5_WOL_ARP = 1 << 3,
MLX5_WOL_BROADCAST = 1 << 4,
MLX5_WOL_MULTICAST = 1 << 5,
MLX5_WOL_UNICAST = 1 << 6,
MLX5_WOL_PHY_ACTIVITY = 1 << 7,
};
/* MLX5 DEV CAPs */
/* TODO: EAT.ME */

62
include/linux/mlx5/mlx5_ifc.h
View File

@@ -166,6 +166,8 @@ enum {
MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
MLX5_CMD_OP_SET_WOL_ROL = 0x830,
MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
MLX5_CMD_OP_CREATE_TIR = 0x900,
MLX5_CMD_OP_MODIFY_TIR = 0x901,
MLX5_CMD_OP_DESTROY_TIR = 0x902,
@@ -731,7 +733,17 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 log_max_msg[0x5];
u8 reserved_at_1c7[0x4];
u8 max_tc[0x4];
u8 reserved_at_1cf[0x10];
u8 reserved_at_1cf[0x6];
u8 rol_s[0x1];
u8 rol_g[0x1];
u8 reserved_at_1d7[0x1];
u8 wol_s[0x1];
u8 wol_g[0x1];
u8 wol_a[0x1];
u8 wol_b[0x1];
u8 wol_m[0x1];
u8 wol_u[0x1];
u8 wol_p[0x1];
u8 stat_rate_support[0x10];
u8 reserved_at_1ef[0xc];
@@ -6873,6 +6885,54 @@ struct mlx5_ifc_mtt_bits {
u8 rd_en[0x1];
};
struct mlx5_ifc_query_wol_rol_out_bits {
u8 status[0x8];
u8 reserved_at_8[0x18];
u8 syndrome[0x20];
u8 reserved_at_40[0x10];
u8 rol_mode[0x8];
u8 wol_mode[0x8];
u8 reserved_at_60[0x20];
};
struct mlx5_ifc_query_wol_rol_in_bits {
u8 opcode[0x10];
u8 reserved_at_10[0x10];
u8 reserved_at_20[0x10];
u8 op_mod[0x10];
u8 reserved_at_40[0x40];
};
struct mlx5_ifc_set_wol_rol_out_bits {
u8 status[0x8];
u8 reserved_at_8[0x18];
u8 syndrome[0x20];
u8 reserved_at_40[0x40];
};
struct mlx5_ifc_set_wol_rol_in_bits {
u8 opcode[0x10];
u8 reserved_at_10[0x10];
u8 reserved_at_20[0x10];
u8 op_mod[0x10];
u8 rol_mode_valid[0x1];
u8 wol_mode_valid[0x1];
u8 reserved_at_42[0xe];
u8 rol_mode[0x8];
u8 wol_mode[0x8];
u8 reserved_at_60[0x20];
};
enum {
MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,

2
include/linux/mlx5/port.h
View File

@@ -81,5 +81,7 @@ int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
u8 *max_bw_value,
u8 *max_bw_unit);
int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode);
int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode);
#endif /* __MLX5_PORT_H__ */