Merge tag 'pci-v4.21-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI updates from Bjorn Helgaas: - Remove unused lists from ASPM pcie_link_state (Frederick Lawler) - Fix Broadcom CNB20LE host bridge unintended sign extension (Colin Ian King) - Expand Kconfig "PF" acronyms (Randy Dunlap) - Update MAINTAINERS for arch/x86/kernel/early-quirks.c (Bjorn Helgaas) - Add missing include to drivers/pci.h (Alexandru Gagniuc) - Override Synopsys USB 3.x HAPS device class so dwc3-haps can claim it instead of xhci (Thinh Nguyen) - Clean up P2PDMA documentation (Randy Dunlap) - Allow runtime PM even if driver doesn't supply callbacks (Jarkko Nikula) - Remove status check after submitting Switchtec MRPC Firmware Download commands to avoid Completion Timeouts (Kelvin Cao) - Set Switchtec coherent DMA mask to allow 64-bit DMA (Boris Glimcher) - Fix Switchtec SWITCHTEC_IOCTL_EVENT_IDX_ALL flag overwrite issue (Joey Zhang) - Enable write combining for Switchtec MRPC Input buffers (Kelvin Cao) - Add Switchtec MRPC DMA mode support (Wesley Sheng) - Skip VF scanning on powerpc, which does this in firmware (Sebastian Ott) - Add Amlogic Meson PCIe controller driver and DT bindings (Yue Wang) - Constify histb dw_pcie_host_ops structure (Julia Lawall) - Support multiple power domains for imx6 (Leonard Crestez) - Constify layerscape driver data (Stefan Agner) - Update imx6 Kconfig to allow imx6 PCIe in imx7 kernel (Trent Piepho) - Support armada8k GPIO reset (Baruch Siach) - Support suspend/resume support on imx6 (Leonard Crestez) - Don't hard-code DesignWare DBI/ATU offst (Stephen Warren) - Skip i.MX6 PHY setup on i.MX7D (Andrey Smirnov) - Remove Jianguo Sun from HiSilicon STB maintainers (Lorenzo Pieralisi) - Mask DesignWare interrupts instead of disabling them to avoid lost interrupts (Marc Zyngier) - Add locking when acking DesignWare interrupts (Marc Zyngier) - Ack DesignWare interrupts in the proper callbacks (Marc Zyngier) - Use devm resource parser in mediatek (Honghui Zhang) - Remove unused mediatek "num-lanes" DT property (Honghui Zhang) - Add UniPhier PCIe controller driver and DT bindings (Kunihiko Hayashi) - Enable MSI for imx6 downstream components (Richard Zhu) * tag 'pci-v4.21-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (40 commits) PCI: imx: Enable MSI from downstream components s390/pci: skip VF scanning PCI/IOV: Add flag so platforms can skip VF scanning PCI/IOV: Factor out sriov_add_vfs() PCI: uniphier: Add UniPhier PCIe host controller support dt-bindings: PCI: Add UniPhier PCIe host controller description PCI: amlogic: Add the Amlogic Meson PCIe controller driver dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller arm64: dts: mt7622: Remove un-used property for PCIe arm: dts: mt7623: Remove un-used property for PCIe dt-bindings: PCI: MediaTek: Remove un-used property PCI: mediatek: Remove un-used variant in struct mtk_pcie_port MAINTAINERS: Remove Jianguo Sun from HiSilicon STB DWC entry PCI: dwc: Don't hard-code DBI/ATU offset PCI: imx: Add imx6sx suspend/resume support PCI: armada8k: Add support for gpio controlled reset signal PCI: dwc: Adjust Kconfig to allow IMX6 PCIe host on IMX7 PCI: dwc: layerscape: Constify driver data PCI: imx: Add multi-pd support PCI: Override Synopsys USB 3.x HAPS device class ...
This commit is contained in:
Linus Torvalds
70
Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
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70
Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
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@@ -0,0 +1,70 @@
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Amlogic Meson AXG DWC PCIE SoC controller
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Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
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It shares common functions with the PCIe DesignWare core driver and
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inherits common properties defined in
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Documentation/devicetree/bindings/pci/designware-pci.txt.
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Additional properties are described here:
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Required properties:
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- compatible:
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should contain "amlogic,axg-pcie" to identify the core.
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- reg:
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should contain the configuration address space.
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- reg-names: Must be
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- "elbi" External local bus interface registers
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- "cfg" Meson specific registers
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- "phy" Meson PCIE PHY registers
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- "config" PCIe configuration space
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- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
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- clocks: Must contain an entry for each entry in clock-names.
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- clock-names: Must include the following entries:
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- "pclk" PCIe GEN 100M PLL clock
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- "port" PCIe_x(A or B) RC clock gate
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- "general" PCIe Phy clock
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- "mipi" PCIe_x(A or B) 100M ref clock gate
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- resets: phandle to the reset lines.
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- reset-names: must contain "phy" "port" and "apb"
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- "phy" Share PHY reset
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- "port" Port A or B reset
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- "apb" Share APB reset
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- device_type:
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should be "pci". As specified in designware-pcie.txt
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Example configuration:
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pcie: pcie@f9800000 {
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compatible = "amlogic,axg-pcie", "snps,dw-pcie";
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reg = <0x0 0xf9800000 0x0 0x400000
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0x0 0xff646000 0x0 0x2000
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0x0 0xff644000 0x0 0x2000
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0x0 0xf9f00000 0x0 0x100000>;
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reg-names = "elbi", "cfg", "phy", "config";
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reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
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interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
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bus-range = <0x0 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>;
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clocks = <&clkc CLKID_USB
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&clkc CLKID_MIPI_ENABLE
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&clkc CLKID_PCIE_A
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&clkc CLKID_PCIE_CML_EN0>;
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clock-names = "general",
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"mipi",
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"pclk",
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"port";
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resets = <&reset RESET_PCIE_PHY>,
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<&reset RESET_PCIE_A>,
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<&reset RESET_PCIE_APB>;
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reset-names = "phy",
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"port",
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"apb";
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};
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@@ -41,7 +41,9 @@ Optional properties:
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Additional required properties for imx6sx-pcie:
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- clock names: Must include the following additional entries:
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- "pcie_inbound_axi"
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- power-domains: Must be set to a phandle pointing to the PCIE_PHY power domain
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- power-domains: Must be set to phandles pointing to the DISPLAY and
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PCIE_PHY power domains
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- power-domain-names: Must be "pcie", "pcie_phy"
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Additional required properties for imx7d-pcie:
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- power-domains: Must be set to a phandle pointing to PCIE_PHY power domain
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@@ -65,7 +65,6 @@ Required properties:
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explanation.
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- ranges: Sub-ranges distributed from the PCIe controller node. An empty
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property is sufficient.
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- num-lanes: Number of lanes to use for this port.
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Examples for MT7623:
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@@ -118,7 +117,6 @@ Examples for MT7623:
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
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ranges;
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num-lanes = <1>;
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};
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pcie@1,0 {
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@@ -129,7 +127,6 @@ Examples for MT7623:
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
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ranges;
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num-lanes = <1>;
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};
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pcie@2,0 {
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@@ -140,7 +137,6 @@ Examples for MT7623:
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
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ranges;
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num-lanes = <1>;
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};
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};
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@@ -172,7 +168,6 @@ Examples for MT2712:
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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num-lanes = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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@@ -191,7 +186,6 @@ Examples for MT2712:
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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num-lanes = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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@@ -245,7 +239,6 @@ Examples for MT7622:
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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num-lanes = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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@@ -264,7 +257,6 @@ Examples for MT7622:
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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num-lanes = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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81
Documentation/devicetree/bindings/pci/uniphier-pcie.txt
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81
Documentation/devicetree/bindings/pci/uniphier-pcie.txt
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@@ -0,0 +1,81 @@
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Socionext UniPhier PCIe host controller bindings
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This describes the devicetree bindings for PCIe host controller implemented
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on Socionext UniPhier SoCs.
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UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core.
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It shares common functions with the PCIe DesignWare core driver and inherits
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common properties defined in
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Documentation/devicetree/bindings/pci/designware-pcie.txt.
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Required properties:
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- compatible: Should be "socionext,uniphier-pcie".
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- reg: Specifies offset and length of the register set for the device.
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According to the reg-names, appropriate register sets are required.
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- reg-names: Must include the following entries:
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"dbi" - controller configuration registers
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"link" - SoC-specific glue layer registers
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"config" - PCIe configuration space
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- clocks: A phandle to the clock gate for PCIe glue layer including
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the host controller.
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- resets: A phandle to the reset line for PCIe glue layer including
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the host controller.
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- interrupts: A list of interrupt specifiers. According to the
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interrupt-names, appropriate interrupts are required.
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- interrupt-names: Must include the following entries:
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"dma" - DMA interrupt
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"msi" - MSI interrupt
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Optional properties:
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- phys: A phandle to generic PCIe PHY. According to the phy-names, appropriate
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phys are required.
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- phy-names: Must be "pcie-phy".
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Required sub-node:
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- legacy-interrupt-controller: Specifies interrupt controller for legacy PCI
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interrupts.
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Required properties for legacy-interrupt-controller:
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- interrupt-controller: identifies the node as an interrupt controller.
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. The value must be 1.
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- interrupt-parent: Phandle to the parent interrupt controller.
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- interrupts: An interrupt specifier for legacy interrupt.
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Example:
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pcie: pcie@66000000 {
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compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
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status = "disabled";
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reg-names = "dbi", "link", "config";
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reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
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<0x2fff0000 0x10000>;
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#address-cells = <3>;
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#size-cells = <2>;
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clocks = <&sys_clk 24>;
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resets = <&sys_rst 24>;
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num-lanes = <1>;
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num-viewport = <1>;
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bus-range = <0x0 0xff>;
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device_type = "pci";
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ranges =
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/* downstream I/O */
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<0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000
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/* non-prefetchable memory */
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0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>;
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#interrupt-cells = <1>;
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interrupt-names = "dma", "msi";
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interrupts = <0 224 4>, <0 225 4>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
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<0 0 0 2 &pcie_intc 1>, /* INTB */
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<0 0 0 3 &pcie_intc 2>, /* INTC */
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<0 0 0 4 &pcie_intc 3>; /* INTD */
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pcie_intc: legacy-interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <0 226 4>;
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};
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};
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