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drm/amd/amdgpu:save psp ring wptr to avoid attack

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[ Upstream commit 2370eba9f552eaae3d8aa1f70b8e9eec5c560f9e ]

[Why]
When some tools performing psp mailbox attack, the readback value
of register can be a random value which may break psp.

[How]
Use a psp wptr cache machanism to aovid the change made by attack.

v2: unify change and add detailed reason

Signed-off-by: Victor Zhao <Victor.Zhao@amd.com>
Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Victor Zhao
2021-03-18 13:44:35 +08:00
committed by Greg Kroah-Hartman
parent 9e8c2af010
commit 9250f97fd5
3 changed files with 5 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
View File

@@ -73,6 +73,7 @@ struct psp_ring
uint64_t ring_mem_mc_addr; uint64_t ring_mem_mc_addr;
void *ring_mem_handle; void *ring_mem_handle;
uint32_t ring_size; uint32_t ring_size;
uint32_t ring_wptr;
}; };
/* More registers may will be supported */ /* More registers may will be supported */

3
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
View File

@@ -732,7 +732,7 @@ static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp)
struct amdgpu_device *adev = psp->adev; struct amdgpu_device *adev = psp->adev;
if (amdgpu_sriov_vf(adev)) if (amdgpu_sriov_vf(adev))
data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); data = psp->km_ring.ring_wptr;
else else
data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
@@ -746,6 +746,7 @@ static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
if (amdgpu_sriov_vf(adev)) { if (amdgpu_sriov_vf(adev)) {
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
psp->km_ring.ring_wptr = value;
} else } else
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
} }

3
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
View File

@@ -379,7 +379,7 @@ static uint32_t psp_v3_1_ring_get_wptr(struct psp_context *psp)
struct amdgpu_device *adev = psp->adev; struct amdgpu_device *adev = psp->adev;
if (amdgpu_sriov_vf(adev)) if (amdgpu_sriov_vf(adev))
data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); data = psp->km_ring.ring_wptr;
else else
data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
return data; return data;
@@ -394,6 +394,7 @@ static void psp_v3_1_ring_set_wptr(struct psp_context *psp, uint32_t value)
/* send interrupt to PSP for SRIOV ring write pointer update */ /* send interrupt to PSP for SRIOV ring write pointer update */
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
GFX_CTRL_CMD_ID_CONSUME_CMD); GFX_CTRL_CMD_ID_CONSUME_CMD);
psp->km_ring.ring_wptr = value;
} else } else
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
} }