drm/i915: Pad GTT views of exec objects up to user specified size
Our GPUs impose certain requirements upon buffers that depend upon how exactly they are used. Typically this is expressed as that they require a larger surface than would be naively computed by pitch * height. Normally such requirements are hidden away in the userspace driver, but when we accept pointers from strangers and later impose extra conditions on them, the original client allocator has no idea about the monstrosities in the GPU and we require the userspace driver to inform the kernel how many padding pages are required beyond the client allocation. v2: Long time, no see v3: Try an anonymous union for uapi struct compatibility Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1470324762-2545-7-git-send-email-chris@chris-wilson.co.uk
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@@ -727,11 +727,15 @@ struct drm_i915_gem_exec_object2 {
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#define EXEC_OBJECT_WRITE (1<<2)
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#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
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#define EXEC_OBJECT_PINNED (1<<4)
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#define EXEC_OBJECT_PAD_TO_SIZE (1<<5)
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/* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
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#define __EXEC_OBJECT_UNKNOWN_FLAGS (-(EXEC_OBJECT_PINNED<<1))
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#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PAD_TO_SIZE<<1)
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__u64 flags;
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__u64 rsvd1;
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union {
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__u64 rsvd1;
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__u64 pad_to_size;
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};
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__u64 rsvd2;
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};
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