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MIPS: Netlogic: move cpu_ready array to boot area

Move the nlm_cpu_ready[] array used by the cpu wakeup code to the
boot area, along with rest of the boot parameter code.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5425/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Este cometimento está contido em:
Jayachandran C
2013-06-10 06:41:04 +00:00
cometido por Ralf Baechle
ascendente 53c832197f
cometimento 919f9abb37
8 ficheiros modificados com 22 adições e 9 eliminações

Ver ficheiro

@@ -216,8 +216,10 @@ EXPORT(nlm_boot_siblings)
ori t1, ST0_KX
#endif
mtc0 t1, CP0_STATUS
/* mark CPU ready */
PTR_LA t1, nlm_cpu_ready
/* mark CPU ready, careful here, previous mtcr trashed registers */
li t3, CKSEG1ADDR(RESET_DATA_PHYS)
ADDIU t1, t3, BOOT_CPU_READY
sll v1, v0, 2
PTR_ADDU t1, v1
li t2, 1

Ver ficheiro

@@ -145,7 +145,6 @@ void nlm_cpus_done(void)
* Boot all other cpus in the system, initialize them, and bring them into
* the boot function
*/
int nlm_cpu_ready[NR_CPUS];
unsigned long nlm_next_gp;
unsigned long nlm_next_sp;
static cpumask_t phys_cpu_present_mask;
@@ -168,6 +167,7 @@ void __init nlm_smp_setup(void)
{
unsigned int boot_cpu;
int num_cpus, i, ncore;
volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
char buf[64];
boot_cpu = hard_smp_processor_id();
@@ -181,10 +181,10 @@ void __init nlm_smp_setup(void)
num_cpus = 1;
for (i = 0; i < NR_CPUS; i++) {
/*
* nlm_cpu_ready array is not set for the boot_cpu,
* cpu_ready array is not set for the boot_cpu,
* it is only set for ASPs (see smpboot.S)
*/
if (nlm_cpu_ready[i]) {
if (cpu_ready[i]) {
cpumask_set_cpu(i, &phys_cpu_present_mask);
__cpu_number_map[i] = num_cpus;
__cpu_logical_map[num_cpus] = i;

Ver ficheiro

@@ -109,8 +109,9 @@ NESTED(nlm_rmiboot_preboot, 16, sp)
andi t2, t0, 0x3 /* thread num */
sll t0, 2 /* offset in cpu array */
PTR_LA t1, nlm_cpu_ready /* mark CPU ready */
PTR_ADDU t1, t0
li t3, CKSEG1ADDR(RESET_DATA_PHYS)
ADDIU t1, t3, BOOT_CPU_READY
ADDU t1, t0
li t3, 1
sw t3, 0(t1)