Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma
Pull rdma updates from Jason Gunthorpe: "The majority of the patches are cleanups, refactorings and clarity improvements. This cycle saw some more activity from Syzkaller, I think we are now clean on all but one of those bugs, including the long standing and obnoxious rdma_cm locking design defect. Continue to see many drivers getting cleanups, with a few new user visible features. Summary: - Various driver updates for siw, bnxt_re, rxe, efa, mlx5, hfi1 - Lots of cleanup patches for hns - Convert more places to use refcount - Aggressively lock the RDMA CM code that syzkaller says isn't working - Work to clarify ib_cm - Use the new ib_device lifecycle model in bnxt_re - Fix mlx5's MR cache which seems to be failing more often with the new ODP code - mlx5 'dynamic uar' and 'tx steering' user interfaces" * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma: (144 commits) RDMA/bnxt_re: make bnxt_re_ib_init static IB/qib: Delete struct qib_ivdev.qp_rnd RDMA/hns: Fix uninitialized variable bug RDMA/hns: Modify the mask of QP number for CQE of hip08 RDMA/hns: Reduce the maximum number of extend SGE per WQE RDMA/hns: Reduce PFC frames in congestion scenarios RDMA/mlx5: Add support for RDMA TX flow table net/mlx5: Add support for RDMA TX steering IB/hfi1: Call kobject_put() when kobject_init_and_add() fails IB/hfi1: Fix memory leaks in sysfs registration and unregistration IB/mlx5: Move to fully dynamic UAR mode once user space supports it IB/mlx5: Limit the scope of struct mlx5_bfreg_info to mlx5_ib IB/mlx5: Extend QP creation to get uar page index from user space IB/mlx5: Extend CQ creation to get uar page index from user space IB/mlx5: Expose UAR object and its alloc/destroy commands IB/hfi1: Get rid of a warning RDMA/hns: Remove redundant judgment of qp_type RDMA/hns: Remove redundant assignment of wc->smac when polling cq RDMA/hns: Remove redundant qpc setup operations RDMA/hns: Remove meaningless prints ...
This commit is contained in:
@@ -49,6 +49,7 @@ enum {
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MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC = 1 << 7,
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MLX5_QP_FLAG_ALLOW_SCATTER_CQE = 1 << 8,
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MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE = 1 << 9,
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MLX5_QP_FLAG_UAR_PAGE_INDEX = 1 << 10,
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};
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enum {
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@@ -78,6 +79,7 @@ struct mlx5_ib_alloc_ucontext_req {
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enum mlx5_lib_caps {
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MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0,
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MLX5_LIB_CAP_DYN_UAR = (__u64)1 << 1,
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};
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enum mlx5_ib_alloc_uctx_v2_flags {
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@@ -266,6 +268,7 @@ struct mlx5_ib_query_device_resp {
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enum mlx5_ib_create_cq_flags {
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MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0,
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MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX = 1 << 1,
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};
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struct mlx5_ib_create_cq {
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@@ -275,6 +278,9 @@ struct mlx5_ib_create_cq {
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__u8 cqe_comp_en;
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__u8 cqe_comp_res_format;
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__u16 flags;
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__u16 uar_page_index;
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__u16 reserved0;
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__u32 reserved1;
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};
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struct mlx5_ib_create_cq_resp {
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@@ -131,6 +131,23 @@ enum mlx5_ib_var_obj_methods {
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MLX5_IB_METHOD_VAR_OBJ_DESTROY,
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};
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enum mlx5_ib_uar_alloc_attrs {
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MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE = (1U << UVERBS_ID_NS_SHIFT),
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MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE,
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MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
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MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
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MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
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};
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enum mlx5_ib_uar_obj_destroy_attrs {
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MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE = (1U << UVERBS_ID_NS_SHIFT),
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};
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enum mlx5_ib_uar_obj_methods {
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MLX5_IB_METHOD_UAR_OBJ_ALLOC = (1U << UVERBS_ID_NS_SHIFT),
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MLX5_IB_METHOD_UAR_OBJ_DESTROY,
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};
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enum mlx5_ib_devx_umem_reg_attrs {
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MLX5_IB_ATTR_DEVX_UMEM_REG_HANDLE = (1U << UVERBS_ID_NS_SHIFT),
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MLX5_IB_ATTR_DEVX_UMEM_REG_ADDR,
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@@ -143,6 +160,22 @@ enum mlx5_ib_devx_umem_dereg_attrs {
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MLX5_IB_ATTR_DEVX_UMEM_DEREG_HANDLE = (1U << UVERBS_ID_NS_SHIFT),
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};
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enum mlx5_ib_pp_obj_methods {
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MLX5_IB_METHOD_PP_OBJ_ALLOC = (1U << UVERBS_ID_NS_SHIFT),
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MLX5_IB_METHOD_PP_OBJ_DESTROY,
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};
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enum mlx5_ib_pp_alloc_attrs {
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MLX5_IB_ATTR_PP_OBJ_ALLOC_HANDLE = (1U << UVERBS_ID_NS_SHIFT),
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MLX5_IB_ATTR_PP_OBJ_ALLOC_CTX,
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MLX5_IB_ATTR_PP_OBJ_ALLOC_FLAGS,
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MLX5_IB_ATTR_PP_OBJ_ALLOC_INDEX,
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};
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enum mlx5_ib_pp_obj_destroy_attrs {
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MLX5_IB_ATTR_PP_OBJ_DESTROY_HANDLE = (1U << UVERBS_ID_NS_SHIFT),
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};
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enum mlx5_ib_devx_umem_methods {
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MLX5_IB_METHOD_DEVX_UMEM_REG = (1U << UVERBS_ID_NS_SHIFT),
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MLX5_IB_METHOD_DEVX_UMEM_DEREG,
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@@ -173,6 +206,8 @@ enum mlx5_ib_objects {
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MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD,
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MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD,
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MLX5_IB_OBJECT_VAR,
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MLX5_IB_OBJECT_PP,
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MLX5_IB_OBJECT_UAR,
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};
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enum mlx5_ib_flow_matcher_create_attrs {
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@@ -44,6 +44,7 @@ enum mlx5_ib_uapi_flow_table_type {
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MLX5_IB_UAPI_FLOW_TABLE_TYPE_NIC_TX = 0x1,
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MLX5_IB_UAPI_FLOW_TABLE_TYPE_FDB = 0x2,
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MLX5_IB_UAPI_FLOW_TABLE_TYPE_RDMA_RX = 0x3,
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MLX5_IB_UAPI_FLOW_TABLE_TYPE_RDMA_TX = 0x4,
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};
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enum mlx5_ib_uapi_flow_action_packet_reformat_type {
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@@ -73,5 +74,14 @@ struct mlx5_ib_uapi_devx_async_event_hdr {
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__u8 out_data[];
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};
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enum mlx5_ib_uapi_pp_alloc_flags {
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MLX5_IB_UAPI_PP_ALLOC_FLAGS_DEDICATED_INDEX = 1 << 0,
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};
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enum mlx5_ib_uapi_uar_alloc_type {
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MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF = 0x0,
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MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC = 0x1,
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};
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#endif
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