Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd: "This round of clk driver and framework updates is heavy on the driver update side. The two main highlights in the core framework are the addition of an bulk clk_get API that handles optional clks and an extra debugfs file that tells the developer about the current parent of a clk. The driver updates are dominated by i.MX in the diffstat, but that is mostly because that SoC has started converting to the clk_hw style of clk registration. The next big update is in the Amlogic meson clk driver that gained some support for audio, cpu, and temperature clks while fixing some PLL issues. Finally, the biggest thing that stands out is the conversion of a large part of the Allwinner sunxi-ng driver to the new clk parent scheme that uses less strings and more pointer comparisons to match clk parents and children up. In general, it looks like we have a lot of little fixes and tweaks here and there to clk data along with the normal addition of a handful of new drivers and a couple new core framework features. Core: - Add a 'clk_parent' file in clk debugfs - Add a clk_bulk_get_optional() API (with devm too) New Drivers: - Support gated clk controller on MIPS based BCM63XX SoCs - Support SiLabs Si5341 and Si5340 chips - Support for CPU clks on Raspberry Pi devices - Audsys clock driver for MediaTek MT8516 SoCs Updates: - Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme - Small frequency support for SiLabs Si544 chips - Slow clk support for AT91 SAM9X60 SoCs - Remove dead code in various clk drivers (-Wunused) - Support for Marvell 98DX1135 SoCs - Get duty cycle of generic pwm clks - Improvement in mmc phase calculation and cleanup of some rate defintions - Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs - Add GPIO, SNVS and GIC clocks for i.MX8 drivers - Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock - Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting - Add clks for new Exynos5422 Dynamic Memory Controller driver - Clock definition for Exynos4412 Mali - Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3 - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M - Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs - TI clock probing done from DT by default instead of firmware - Fix Amlogic Meson mpll fractional part and spread sprectrum issues - Add Amlogic meson8 audio clocks - Add Amlogic g12a temperature sensors clocks - Add Amlogic g12a and g12b cpu clocks - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N - Add CMM (Color Management Module) clocks on Renesas R-Car M3-W - Add Clock Domain support on Renesas RZ/N1" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (190 commits) clk: consoldiate the __clk_get_hw() declarations clk: sprd: Add check for return value of sprd_clk_regmap_init() clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK clk: Add Si5341/Si5340 driver dt-bindings: clock: Add silabs,si5341 clk: clk-si544: Implement small frequency change support clk: add BCM63XX gated clock controller driver devicetree: document the BCM63XX gated clock bindings clk: at91: sckc: use dedicated functions to unregister clock clk: at91: sckc: improve error path for sama5d4 sck registration clk: at91: sckc: remove unnecessary line clk: at91: sckc: improve error path for sam9x5 sck register clk: at91: sckc: add support to free slow clock osclillator clk: at91: sckc: add support to free slow rc oscillator clk: at91: sckc: add support to free slow oscillator clk: rockchip: export HDMIPHY clock on rk3228 clk: rockchip: add watchdog pclk on rk3328 clk: rockchip: add clock id for hdmi_phy special clock on rk3228 clk: rockchip: add clock id for watchdog pclk on rk3328 clk: at91: sckc: add support for SAM9X60 ...
This commit is contained in:
Linus Torvalds
@@ -10,6 +10,7 @@ Required Properties:
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- "mediatek,mt7622-audsys", "syscon"
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- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
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- "mediatek,mt8183-audiosys", "syscon"
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- "mediatek,mt8516-audsys", "syscon"
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- #clock-cells: Must be 1
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The AUDSYS controller uses the common clk binding from
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@@ -0,0 +1,141 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/allwinner,sun4i-a10-ccu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner Clock Control Unit Device Tree Bindings
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>
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- Maxime Ripard <maxime.ripard@bootlin.com>
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properties:
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"#clock-cells":
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const: 1
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"#reset-cells":
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const: 1
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compatible:
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enum:
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- allwinner,sun4i-a10-ccu
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- allwinner,sun5i-a10s-ccu
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- allwinner,sun5i-a13-ccu
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- allwinner,sun6i-a31-ccu
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- allwinner,sun7i-a20-ccu
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- allwinner,sun8i-a23-ccu
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- allwinner,sun8i-a33-ccu
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- allwinner,sun8i-a83t-ccu
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- allwinner,sun8i-a83t-r-ccu
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- allwinner,sun8i-h3-ccu
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- allwinner,sun8i-h3-r-ccu
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- allwinner,sun8i-r40-ccu
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- allwinner,sun8i-v3s-ccu
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- allwinner,sun9i-a80-ccu
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- allwinner,sun50i-a64-ccu
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- allwinner,sun50i-a64-r-ccu
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- allwinner,sun50i-h5-ccu
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- allwinner,sun50i-h6-ccu
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- allwinner,sun50i-h6-r-ccu
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- allwinner,suniv-f1c100s-ccu
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- nextthing,gr8-ccu
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reg:
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maxItems: 1
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clocks:
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minItems: 2
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maxItems: 4
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items:
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- description: High Frequency Oscillator (usually at 24MHz)
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- description: Low Frequency Oscillator (usually at 32kHz)
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- description: Internal Oscillator
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- description: Peripherals PLL
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clock-names:
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minItems: 2
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maxItems: 4
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items:
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- const: hosc
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- const: losc
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- const: iosc
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- const: pll-periph
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required:
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- "#clock-cells"
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- "#reset-cells"
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- compatible
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- reg
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- clocks
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- clock-names
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if:
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properties:
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compatible:
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enum:
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- allwinner,sun8i-a83t-r-ccu
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- allwinner,sun8i-h3-r-ccu
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- allwinner,sun50i-a64-r-ccu
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- allwinner,sun50i-h6-r-ccu
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then:
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properties:
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clocks:
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minItems: 4
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maxItems: 4
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clock-names:
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minItems: 4
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maxItems: 4
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else:
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if:
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properties:
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compatible:
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const: allwinner,sun50i-h6-ccu
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then:
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properties:
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clocks:
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minItems: 3
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maxItems: 3
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clock-names:
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minItems: 3
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maxItems: 3
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else:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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minItems: 2
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maxItems: 2
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additionalProperties: false
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|
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examples:
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- |
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ccu: clock@1c20000 {
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compatible = "allwinner,sun8i-h3-ccu";
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reg = <0x01c20000 0x400>;
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clocks = <&osc24M>, <&osc32k>;
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clock-names = "hosc", "losc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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- |
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r_ccu: clock@1f01400 {
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compatible = "allwinner,sun50i-a64-r-ccu";
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reg = <0x01f01400 0x100>;
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clocks = <&osc24M>, <&osc32k>, <&iosc>, <&ccu 11>;
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clock-names = "hosc", "losc", "iosc", "pll-periph";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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...
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@@ -10,6 +10,7 @@ Required Properties:
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"amlogic,gxl-clkc" for GXL and GXM SoC,
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"amlogic,axg-clkc" for AXG SoC.
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"amlogic,g12a-clkc" for G12A SoC.
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"amlogic,g12b-clkc" for G12B SoC.
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- clocks : list of clock phandle, one for each entry clock-names.
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- clock-names : should contain the following:
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* "xtal": the platform xtal
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@@ -9,10 +9,11 @@ Slow Clock controller:
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Required properties:
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- compatible : shall be one of the following:
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"atmel,at91sam9x5-sckc",
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"atmel,sama5d3-sckc" or
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"atmel,sama5d4-sckc":
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"atmel,sama5d3-sckc",
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"atmel,sama5d4-sckc" or
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"microchip,sam9x60-sckc":
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at91 SCKC (Slow Clock Controller)
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- #clock-cells : shall be 0.
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- #clock-cells : shall be 1 for "microchip,sam9x60-sckc" otherwise shall be 0.
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- clocks : shall be the input parent clock phandle for the clock.
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Optional properties:
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|
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@@ -0,0 +1,22 @@
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Gated Clock Controller Bindings for MIPS based BCM63XX SoCs
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|
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Required properties:
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- compatible: must be one of:
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"brcm,bcm3368-clocks"
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"brcm,bcm6328-clocks"
|
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"brcm,bcm6358-clocks"
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"brcm,bcm6362-clocks"
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"brcm,bcm6368-clocks"
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"brcm,bcm63268-clocks"
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- reg: Address and length of the register set
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- #clock-cells: must be <1>
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|
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Example:
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clkctl: clock-controller@10000004 {
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compatible = "brcm,bcm6328-clocks";
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reg = <0x10000004 0x4>;
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#clock-cells = <1>;
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};
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@@ -40,6 +40,7 @@ Optional properties:
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input audio clocks from host system.
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- ln-psia1-mclk, ln-psia2-mclk : Optional input audio clocks from
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external connector.
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- ln-spdif-mclk : Optional input audio clock from SPDIF.
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- ln-spdif-clkout : Optional input audio clock from SPDIF.
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- ln-adat-mclk : Optional input audio clock from ADAT.
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- ln-pmic-32k : On board fixed clock.
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@@ -59,6 +59,7 @@ Required properties:
|
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"marvell,dove-core-clock" - for Dove SoC core clocks
|
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"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
|
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"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
|
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"marvell,mv98dx1135-core-clock" - for Kirkwood 98dx1135 SoC
|
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"marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC
|
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"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
|
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"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
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|
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@@ -2,13 +2,15 @@ Qualcomm Graphics Clock & Reset Controller Binding
|
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--------------------------------------------------
|
||||
|
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Required properties :
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- compatible : shall contain "qcom,sdm845-gpucc"
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- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc"
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- reg : shall contain base register location and length
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- #clock-cells : from common clock binding, shall contain 1
|
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- #reset-cells : from common reset binding, shall contain 1
|
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- #power-domain-cells : from generic power domain binding, shall contain 1
|
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- clocks : shall contain the XO clock
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shall contain the gpll0 out main clock (msm8998)
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- clock-names : shall be "xo"
|
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shall be "gpll0" (msm8998)
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|
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Example:
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gpucc: clock-controller@5090000 {
|
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|
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@@ -13,6 +13,7 @@ Required Properties:
|
||||
- external (optional) RGMII_REFCLK
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- clock-names: Must be:
|
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clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
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- #power-domain-cells: Must be 0
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Examples
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--------
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||||
@@ -27,6 +28,7 @@ Examples
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clocks = <&ext_mclk>, <&ext_rtc_clk>,
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<&ext_jtag_clk>, <&ext_rgmii_ref>;
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clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
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#power-domain-cells = <0>;
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};
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- Other nodes can use the clocks provided by SYSCTRL as in:
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@@ -38,6 +40,7 @@ Examples
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
|
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clocks = <&sysctrl R9A06G032_CLK_UART0>;
|
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clock-names = "baudclk";
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clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
|
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clock-names = "baudclk", "apb_pclk";
|
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power-domains = <&sysctrl>;
|
||||
};
|
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|
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162
Documentation/devicetree/bindings/clock/silabs,si5341.txt
Normal file
162
Documentation/devicetree/bindings/clock/silabs,si5341.txt
Normal file
@@ -0,0 +1,162 @@
|
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Binding for Silicon Labs Si5341 and Si5340 programmable i2c clock generator.
|
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|
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Reference
|
||||
[1] Si5341 Data Sheet
|
||||
https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
|
||||
[2] Si5341 Reference Manual
|
||||
https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
|
||||
|
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The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
|
||||
clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
|
||||
in turn can be directed to any of the 10 (or 4) outputs through a divider.
|
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The internal structure of the clock generators can be found in [2].
|
||||
|
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The driver can be used in "as is" mode, reading the current settings from the
|
||||
chip at boot, in case you have a (pre-)programmed device. If the PLL is not
|
||||
configured when the driver probes, it assumes the driver must fully initialize
|
||||
it.
|
||||
|
||||
The device type, speed grade and revision are determined runtime by probing.
|
||||
|
||||
The driver currently only supports XTAL input mode, and does not support any
|
||||
fancy input configurations. They can still be programmed into the chip and
|
||||
the driver will leave them "as is".
|
||||
|
||||
==I2C device node==
|
||||
|
||||
Required properties:
|
||||
- compatible: shall be one of the following:
|
||||
"silabs,si5340" - Si5340 A/B/C/D
|
||||
"silabs,si5341" - Si5341 A/B/C/D
|
||||
- reg: i2c device address, usually 0x74
|
||||
- #clock-cells: from common clock binding; shall be set to 2.
|
||||
The first value is "0" for outputs, "1" for synthesizers.
|
||||
The second value is the output or synthesizer index.
|
||||
- clocks: from common clock binding; list of parent clock handles,
|
||||
corresponding to inputs. Use a fixed clock for the "xtal" input.
|
||||
At least one must be present.
|
||||
- clock-names: One of: "xtal", "in0", "in1", "in2"
|
||||
- vdd-supply: Regulator node for VDD
|
||||
|
||||
Optional properties:
|
||||
- vdda-supply: Regulator node for VDDA
|
||||
- vdds-supply: Regulator node for VDDS
|
||||
- silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL
|
||||
feedback divider. Must be such that the PLL output is in the valid range. For
|
||||
example, to create 14GHz from a 48MHz xtal, use m-num=14000 and m-den=48. Only
|
||||
the fraction matters, using 3500 and 12 will deliver the exact same result.
|
||||
If these are not specified, and the PLL is not yet programmed when the driver
|
||||
probes, the PLL will be set to 14GHz.
|
||||
- silabs,reprogram: When present, the driver will always assume the device must
|
||||
be initialized, and always performs the soft-reset routine. Since this will
|
||||
temporarily stop all output clocks, don't do this if the chip is generating
|
||||
the CPU clock for example.
|
||||
- interrupts: Interrupt for INTRb pin.
|
||||
- #address-cells: shall be set to 1.
|
||||
- #size-cells: shall be set to 0.
|
||||
|
||||
|
||||
== Child nodes: Outputs ==
|
||||
|
||||
The child nodes list the output clocks.
|
||||
|
||||
Each of the clock outputs can be overwritten individually by using a child node.
|
||||
If a child node for a clock output is not set, the configuration remains
|
||||
unchanged.
|
||||
|
||||
Required child node properties:
|
||||
- reg: number of clock output.
|
||||
|
||||
Optional child node properties:
|
||||
- vdd-supply: Regulator node for VDD for this output. The driver selects default
|
||||
values for common-mode and amplitude based on the voltage.
|
||||
- silabs,format: Output format, one of:
|
||||
1 = differential (defaults to LVDS levels)
|
||||
2 = low-power (defaults to HCSL levels)
|
||||
4 = LVCMOS
|
||||
- silabs,common-mode: Manually override output common mode, see [2] for values
|
||||
- silabs,amplitude: Manually override output amplitude, see [2] for values
|
||||
- silabs,synth-master: boolean. If present, this output is allowed to change the
|
||||
multisynth frequency dynamically.
|
||||
- silabs,silabs,disable-high: boolean. If set, the clock output is driven HIGH
|
||||
when disabled, otherwise it's driven LOW.
|
||||
|
||||
==Example==
|
||||
|
||||
/* 48MHz reference crystal */
|
||||
ref48: ref48M {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
i2c-master-node {
|
||||
/* Programmable clock (for logic) */
|
||||
si5341: clock-generator@74 {
|
||||
reg = <0x74>;
|
||||
compatible = "silabs,si5341";
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&ref48>;
|
||||
clock-names = "xtal";
|
||||
|
||||
silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
|
||||
silabs,pll-m-den = <48>;
|
||||
silabs,reprogram; /* Chips are not programmed, always reset */
|
||||
|
||||
out@0 {
|
||||
reg = <0>;
|
||||
silabs,format = <1>; /* LVDS 3v3 */
|
||||
silabs,common-mode = <3>;
|
||||
silabs,amplitude = <3>;
|
||||
silabs,synth-master;
|
||||
};
|
||||
|
||||
/*
|
||||
* Output 6 configuration:
|
||||
* LVDS 1v8
|
||||
*/
|
||||
out@6 {
|
||||
reg = <6>;
|
||||
silabs,format = <1>; /* LVDS 1v8 */
|
||||
silabs,common-mode = <13>;
|
||||
silabs,amplitude = <3>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Output 8 configuration:
|
||||
* HCSL 3v3
|
||||
*/
|
||||
out@8 {
|
||||
reg = <8>;
|
||||
silabs,format = <2>;
|
||||
silabs,common-mode = <11>;
|
||||
silabs,amplitude = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
some-video-node {
|
||||
/* Standard clock bindings */
|
||||
clock-names = "pixel";
|
||||
clocks = <&si5341 0 7>; /* Output 7 */
|
||||
|
||||
/* Set output 7 to use syntesizer 3 as its parent */
|
||||
assigned-clocks = <&si5341 0 7>, <&si5341 1 3>;
|
||||
assigned-clock-parents = <&si5341 1 3>;
|
||||
/* Set output 7 to 148.5 MHz using a synth frequency of 594 MHz */
|
||||
assigned-clock-rates = <148500000>, <594000000>;
|
||||
};
|
||||
|
||||
some-audio-node {
|
||||
clock-names = "i2s-clk";
|
||||
clocks = <&si5341 0 0>;
|
||||
/*
|
||||
* since output 0 is a synth-master, the synth will be automatically set
|
||||
* to an appropriate frequency when the audio driver requests another
|
||||
* frequency. We give control over synth 2 to this output here.
|
||||
*/
|
||||
assigned-clocks = <&si5341 0 0>;
|
||||
assigned-clock-parents = <&si5341 1 2>;
|
||||
};
|
||||
@@ -1,62 +0,0 @@
|
||||
Allwinner Clock Control Unit Binding
|
||||
------------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible: must contain one of the following compatibles:
|
||||
- "allwinner,sun4i-a10-ccu"
|
||||
- "allwinner,sun5i-a10s-ccu"
|
||||
- "allwinner,sun5i-a13-ccu"
|
||||
- "allwinner,sun6i-a31-ccu"
|
||||
- "allwinner,sun7i-a20-ccu"
|
||||
- "allwinner,sun8i-a23-ccu"
|
||||
- "allwinner,sun8i-a33-ccu"
|
||||
- "allwinner,sun8i-a83t-ccu"
|
||||
- "allwinner,sun8i-a83t-r-ccu"
|
||||
- "allwinner,sun8i-h3-ccu"
|
||||
- "allwinner,sun8i-h3-r-ccu"
|
||||
+ - "allwinner,sun8i-r40-ccu"
|
||||
- "allwinner,sun8i-v3s-ccu"
|
||||
- "allwinner,sun9i-a80-ccu"
|
||||
- "allwinner,sun50i-a64-ccu"
|
||||
- "allwinner,sun50i-a64-r-ccu"
|
||||
- "allwinner,sun50i-h5-ccu"
|
||||
- "allwinner,sun50i-h6-ccu"
|
||||
- "allwinner,sun50i-h6-r-ccu"
|
||||
- "allwinner,suniv-f1c100s-ccu"
|
||||
- "nextthing,gr8-ccu"
|
||||
|
||||
- reg: Must contain the registers base address and length
|
||||
- clocks: phandle to the oscillators feeding the CCU. Two are needed:
|
||||
- "hosc": the high frequency oscillator (usually at 24MHz)
|
||||
- "losc": the low frequency oscillator (usually at 32kHz)
|
||||
On the A83T, this is the internal 16MHz oscillator divided by 512
|
||||
- clock-names: Must contain the clock names described just above
|
||||
- #clock-cells : must contain 1
|
||||
- #reset-cells : must contain 1
|
||||
|
||||
For the main CCU on H6, one more clock is needed:
|
||||
- "iosc": the SoC's internal frequency oscillator
|
||||
|
||||
For the PRCM CCUs on A83T/H3/A64/H6, two more clocks are needed:
|
||||
- "pll-periph": the SoC's peripheral PLL from the main CCU
|
||||
- "iosc": the SoC's internal frequency oscillator
|
||||
|
||||
Example for generic CCU:
|
||||
ccu: clock@1c20000 {
|
||||
compatible = "allwinner,sun8i-h3-ccu";
|
||||
reg = <0x01c20000 0x400>;
|
||||
clocks = <&osc24M>, <&osc32k>;
|
||||
clock-names = "hosc", "losc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example for PRCM CCU:
|
||||
r_ccu: clock@1f01400 {
|
||||
compatible = "allwinner,sun50i-a64-r-ccu";
|
||||
reg = <0x01f01400 0x100>;
|
||||
clocks = <&osc24M>, <&osc32k>, <&iosc>, <&ccu CLK_PLL_PERIPH0>;
|
||||
clock-names = "hosc", "losc", "iosc", "pll-periph";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@@ -246,6 +246,10 @@ CLOCK
|
||||
devm_clk_get()
|
||||
devm_clk_get_optional()
|
||||
devm_clk_put()
|
||||
devm_clk_bulk_get()
|
||||
devm_clk_bulk_get_all()
|
||||
devm_clk_bulk_get_optional()
|
||||
devm_get_clk_from_childl()
|
||||
devm_clk_hw_register()
|
||||
devm_of_clk_add_hw_provider()
|
||||
devm_clk_hw_register_clkdev()
|
||||
|
||||
Reference in New Issue
Block a user