Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Arnd Bergmann: "The arm64 device tree changes make up an increasing portion of the overall changes, so they are kept separate from the 32-bit devicetree changes and from the other arm64 updates. Newly added SoCs and boards are: - 96Boards Husky board - AMD Overdrive board - Amlogic S905 SoC and related Tronsmart boxes - Annapurna Labs Alpine family and development board - Broadcom Vulcan servers - Broadcom Northstar 2 SoC - Marvell Armada 3700 family and development board - Qualcomm MSM8996 SoC Additional devices are enabled for existing platforms from Applied Micro, Hisilicon, Mediatek, Qualcomm, and Renesas and there are a couple of other updates for Rockchip, Xilinx and NXP/Freescale" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (102 commits) ARM64: dts: amlogic: Add Tronsmart Vega S95 configs Documentation: devicetree: amlogic: Document Tronsmart Vega S95 boards ARM64: dts: Prepare configs for Amlogic Meson GXBaby Documentation: devicetree: amlogic: Document Meson GXBaby devicetree: bindings: Add vendor prefix for Tronsmart arm64: dts: qcom: Fix MPP's function used for LED control arm64: dts: alpine: add the MSIX node in the Alpine v2 dtsi arm64: dts: add the Alpine v2 EVP arm64: dts: marvell: re-order Device Tree nodes for Armada AP806 arm64: dts: marvell: update Armada AP806 clock description arm64: dts: marvell: add Device Tree files for Armada 7K/8K arm64: dts: apm: Add DT node for X-Gene v2 SLIMpro Mailbox I2C Driver arm64: dts: apm: Mailbox device tree node for APM X-Gene v2 platform. arm64: dts: apm: Add DT node for X-Gene v1 SLIMpro Mailbox I2C Driver arm64: dts: apm: mailbox device tree node for APM X-Gene platform. arm64: dts: apm: Update GPIO to control power-off on X-Gene v2 platforms arm64: dts: apm: Update GPIO standby controller DT node for X-Gene v2 platforms arm64: dts: apm: Update GPIO to control power-off on X-Gene v1 platforms arm64: dts: salvator-x: enable USB 2.0 Host of channel 1 and 2 arm64: dts: salvator-x: enable usb2_phy of channel 1 and 2 ...
This commit is contained in:
Linus Torvalds
@@ -52,6 +52,14 @@
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};
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};
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&pcie0 {
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status = "ok";
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};
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&pcie4 {
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status = "ok";
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};
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&i2c0 {
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status = "ok";
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};
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@@ -64,6 +72,10 @@
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status = "ok";
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};
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&sdio0 {
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status = "ok";
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};
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&nand {
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nandcs@0 {
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compatible = "brcm,nandcs";
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@@ -137,6 +137,80 @@
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};
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};
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pcie0: pcie@20020000 {
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compatible = "brcm,iproc-pcie";
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reg = <0 0x20020000 0 0x1000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 281 IRQ_TYPE_NONE>;
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
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brcm,pcie-ob;
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brcm,pcie-ob-oarr-size;
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brcm,pcie-ob-axi-offset = <0x00000000>;
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brcm,pcie-ob-window-size = <256>;
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status = "disabled";
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msi-parent = <&msi0>;
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msi0: msi@20020000 {
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compatible = "brcm,iproc-msi";
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msi-controller;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 277 IRQ_TYPE_NONE>,
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<GIC_SPI 278 IRQ_TYPE_NONE>,
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<GIC_SPI 279 IRQ_TYPE_NONE>,
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<GIC_SPI 280 IRQ_TYPE_NONE>;
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brcm,num-eq-region = <1>;
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brcm,num-msi-msg-region = <1>;
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};
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};
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pcie4: pcie@50020000 {
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compatible = "brcm,iproc-pcie";
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reg = <0 0x50020000 0 0x1000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 305 IRQ_TYPE_NONE>;
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linux,pci-domain = <4>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
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brcm,pcie-ob;
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brcm,pcie-ob-oarr-size;
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brcm,pcie-ob-axi-offset = <0x30000000>;
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brcm,pcie-ob-window-size = <256>;
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status = "disabled";
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msi-parent = <&msi4>;
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msi4: msi@50020000 {
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compatible = "brcm,iproc-msi";
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msi-controller;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 301 IRQ_TYPE_NONE>,
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<GIC_SPI 302 IRQ_TYPE_NONE>,
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<GIC_SPI 303 IRQ_TYPE_NONE>,
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<GIC_SPI 304 IRQ_TYPE_NONE>;
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};
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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@@ -256,6 +330,46 @@
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<0x65260000 0x1000>;
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};
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timer0: timer@66030000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x66030000 0x1000>;
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interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>,
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<&iprocslow>,
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<&iprocslow>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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timer1: timer@66040000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x66040000 0x1000>;
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interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>,
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<&iprocslow>,
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<&iprocslow>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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timer2: timer@66050000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x66050000 0x1000>;
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interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>,
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<&iprocslow>,
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<&iprocslow>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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timer3: timer@66060000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x66060000 0x1000>;
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interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>,
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<&iprocslow>,
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<&iprocslow>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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i2c0: i2c@66080000 {
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compatible = "brcm,iproc-i2c";
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reg = <0x66080000 0x100>;
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@@ -266,6 +380,14 @@
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status = "disabled";
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};
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wdt0: watchdog@66090000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x66090000 0x1000>;
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interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>, <&iprocslow>;
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clock-names = "wdogclk", "apb_pclk";
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};
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i2c1: i2c@660b0000 {
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compatible = "brcm,iproc-i2c";
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reg = <0x660b0000 0x100>;
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@@ -291,6 +413,24 @@
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reg = <0x66220000 0x28>;
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};
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sdio0: sdhci@66420000 {
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compatible = "brcm,sdhci-iproc-cygnus";
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reg = <0x66420000 0x100>;
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interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
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bus-width = <8>;
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clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
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status = "disabled";
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};
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sdio1: sdhci@66430000 {
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compatible = "brcm,sdhci-iproc-cygnus";
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reg = <0x66430000 0x100>;
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interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
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bus-width = <8>;
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clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
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status = "disabled";
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};
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nand: nand@66460000 {
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compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
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reg = <0x66460000 0x600>,
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