scsi: mpt3sas: Updated MPI headers to v2.00.48
Updated MPI headers to v2.00.48 Signed-off-by: Sreekanth Reddy <Sreekanth.Reddy@broadcom.com> Reviewed-by: Tomas Henzl <thenzl@redhat.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Sreekanth Reddy
committed by
Martin K. Petersen
Martin K. Petersen
parent
2ce9a36452
commit
90e7a70199
@@ -6,7 +6,7 @@
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* Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
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* Creation Date: October 11, 2006
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*
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* mpi2_ioc.h Version: 02.00.27
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* mpi2_ioc.h Version: 02.00.32
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*
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* NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
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* prefix are for use only on MPI v2.5 products, and must not be used
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@@ -140,7 +140,32 @@
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* Added MPI26_FW_HEADER_PID_FAMILY_3324_SAS and
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* MPI26_FW_HEADER_PID_FAMILY_3516_SAS.
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* Added MPI26_CTRL_OP_SHUTDOWN.
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* 08-25-15 02.00.27 Added IC ARCH Class based signature defines
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* 08-25-15 02.00.27 Added IC ARCH Class based signature defines.
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* Added MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED event.
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* Added ConigurationFlags field to IOCInit message to
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* support NVMe SGL format control.
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* Added PCIe SRIOV support.
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* 02-17-16 02.00.28 Added SAS 4 22.5 gbs speed support.
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* Added PCIe 4 16.0 GT/sec speec support.
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* Removed AHCI support.
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* Removed SOP support.
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* 07-01-16 02.00.29 Added Archclass for 4008 product.
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* Added IOCException MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED
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* 08-23-16 02.00.30 Added new defines for the ImageType field of FWDownload
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* Request Message.
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* Added new defines for the ImageType field of FWUpload
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* Request Message.
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* Added new values for the RegionType field in the Layout
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* Data sections of the FLASH Layout Extended Image Data.
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* Added new defines for the ReasonCode field of
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* Active Cable Exception Event.
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* Added MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE and
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* MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE.
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* 11-23-16 02.00.31 Added MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR and
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* MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR.
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* 02-02-17 02.00.32 Added MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP.
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* Added MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT and related
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* defines for the ReasonCode field.
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* --------------------------------------------------------------------------
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*/
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@@ -212,6 +237,9 @@ typedef struct _MPI2_IOC_INIT_REQUEST {
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#define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
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#define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
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/*ConfigurationFlags */
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#define MPI26_IOCINIT_CFGFLAGS_NVME_SGL_FORMAT (0x0001)
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/*minimum depth for a Reply Descriptor Post Queue */
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#define MPI2_RDPQ_DEPTH_MIN (16)
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@@ -299,6 +327,10 @@ typedef struct _MPI2_IOC_FACTS_REPLY {
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U16 MinDevHandle; /*0x3C */
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U8 CurrentHostPageSize; /* 0x3E */
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U8 Reserved4; /* 0x3F */
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U8 SGEModifierMask; /*0x40 */
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U8 SGEModifierValue; /*0x41 */
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U8 SGEModifierShift; /*0x42 */
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U8 Reserved5; /*0x43 */
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} MPI2_IOC_FACTS_REPLY, *PTR_MPI2_IOC_FACTS_REPLY,
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Mpi2IOCFactsReply_t, *pMpi2IOCFactsReply_t;
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@@ -315,6 +347,7 @@ typedef struct _MPI2_IOC_FACTS_REPLY {
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#define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
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/*IOCExceptions */
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#define MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0400)
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#define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0200)
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#define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
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@@ -335,6 +368,7 @@ typedef struct _MPI2_IOC_FACTS_REPLY {
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/*ProductID field uses MPI2_FW_HEADER_PID_ */
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/*IOCCapabilities */
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#define MPI26_IOCFACTS_CAPABILITY_PCIE_SRIOV (0x00100000)
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#define MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ (0x00080000)
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#define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE (0x00040000)
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#define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000)
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@@ -353,6 +387,7 @@ typedef struct _MPI2_IOC_FACTS_REPLY {
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#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
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/*ProtocolFlags */
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#define MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES (0x0008)
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#define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
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#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
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@@ -402,6 +437,8 @@ typedef struct _MPI2_PORT_FACTS_REPLY {
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#define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)
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#define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)
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#define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)
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#define MPI2_PORTFACTS_PORTTYPE_TRI_MODE (0x40)
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/****************************************************************************
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* PortEnable message
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@@ -508,6 +545,7 @@ typedef struct _MPI2_EVENT_NOTIFICATION_REPLY {
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#define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
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#define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
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#define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
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#define MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE (0x001D)
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#define MPI2_EVENT_IR_VOLUME (0x001E)
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#define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
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#define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
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@@ -520,7 +558,12 @@ typedef struct _MPI2_EVENT_NOTIFICATION_REPLY {
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#define MPI2_EVENT_TEMP_THRESHOLD (0x0027)
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#define MPI2_EVENT_HOST_MESSAGE (0x0028)
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#define MPI2_EVENT_POWER_PERFORMANCE_CHANGE (0x0029)
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#define MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE (0x0030)
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#define MPI2_EVENT_PCIE_ENUMERATION (0x0031)
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#define MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x0032)
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#define MPI2_EVENT_PCIE_LINK_COUNTER (0x0033)
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#define MPI2_EVENT_ACTIVE_CABLE_EXCEPTION (0x0034)
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#define MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR (0x0035)
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#define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E)
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#define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F)
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@@ -617,11 +660,20 @@ typedef struct _MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT {
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U8 ReasonCode; /* 0x04 */
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U8 ReceptacleID; /* 0x05 */
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U16 Reserved1; /* 0x06 */
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} MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
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} MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
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*PTR_MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
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Mpi25EventDataActiveCableExcept_t,
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*pMpi25EventDataActiveCableExcept_t,
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MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
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*PTR_MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
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Mpi26EventDataActiveCableExcept_t,
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*pMpi26EventDataActiveCableExcept_t;
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/*MPI2.5 defines for the ReasonCode field */
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#define MPI25_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00)
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#define MPI25_EVENT_ACTIVE_CABLE_PRESENT (0x01)
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#define MPI25_EVENT_ACTIVE_CABLE_DEGRADED (0x02)
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/* defines for ReasonCode field */
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#define MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00)
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#define MPI26_EVENT_ACTIVE_CABLE_PRESENT (0x01)
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@@ -957,6 +1009,7 @@ typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST {
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#define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
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#define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
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#define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B)
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#define MPI26_EVENT_SAS_TOPO_LR_RATE_22_5 (0x0C)
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/*values for the PhyStatus field */
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#define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
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@@ -982,12 +1035,37 @@ typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE {
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} MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
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*PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
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Mpi2EventDataSasEnclDevStatusChange_t,
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*pMpi2EventDataSasEnclDevStatusChange_t;
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*pMpi2EventDataSasEnclDevStatusChange_t,
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MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE,
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*PTR_MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE,
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Mpi26EventDataEnclDevStatusChange_t,
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*pMpi26EventDataEnclDevStatusChange_t;
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/*SAS Enclosure Device Status Change event ReasonCode values */
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#define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)
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#define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)
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/*Enclosure Device Status Change event ReasonCode values */
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#define MPI26_EVENT_ENCL_RC_ADDED (0x01)
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#define MPI26_EVENT_ENCL_RC_NOT_RESPONDING (0x02)
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typedef struct _MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR {
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U16 DevHandle; /*0x00 */
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U8 ReasonCode; /*0x02 */
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U8 PhysicalPort; /*0x03 */
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U32 Reserved1[2]; /*0x04 */
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U64 SASAddress; /*0x0C */
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U32 Reserved2[2]; /*0x14 */
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} MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR,
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*PTR_MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR,
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Mpi25EventDataSasDeviceDiscoveryError_t,
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*pMpi25EventDataSasDeviceDiscoveryError_t;
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/*SAS Device Discovery Error Event data ReasonCode values */
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#define MPI25_EVENT_SAS_DISC_ERR_SMP_FAILED (0x01)
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#define MPI25_EVENT_SAS_DISC_ERR_SMP_TIMEOUT (0x02)
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/*SAS PHY Counter Event data */
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typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {
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@@ -1073,6 +1151,174 @@ typedef struct _MPI2_EVENT_DATA_HBD_PHY {
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/*values for the DescriptorType field */
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#define MPI2_EVENT_HBD_DT_SAS (0x01)
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/*PCIe Device Status Change Event data (MPI v2.6 and later) */
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typedef struct _MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE {
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U16 TaskTag; /*0x00 */
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U8 ReasonCode; /*0x02 */
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U8 PhysicalPort; /*0x03 */
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U8 ASC; /*0x04 */
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U8 ASCQ; /*0x05 */
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U16 DevHandle; /*0x06 */
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U32 Reserved2; /*0x08 */
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U64 WWID; /*0x0C */
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U8 LUN[8]; /*0x14 */
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} MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE,
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*PTR_MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE,
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Mpi26EventDataPCIeDeviceStatusChange_t,
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*pMpi26EventDataPCIeDeviceStatusChange_t;
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/*PCIe Device Status Change Event data ReasonCode values */
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#define MPI26_EVENT_PCIDEV_STAT_RC_SMART_DATA (0x05)
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#define MPI26_EVENT_PCIDEV_STAT_RC_UNSUPPORTED (0x07)
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#define MPI26_EVENT_PCIDEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
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#define MPI26_EVENT_PCIDEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
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#define MPI26_EVENT_PCIDEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
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#define MPI26_EVENT_PCIDEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
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#define MPI26_EVENT_PCIDEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
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#define MPI26_EVENT_PCIDEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
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#define MPI26_EVENT_PCIDEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
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#define MPI26_EVENT_PCIDEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
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#define MPI26_EVENT_PCIDEV_STAT_RC_DEV_INIT_FAILURE (0x10)
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/*PCIe Enumeration Event data (MPI v2.6 and later) */
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typedef struct _MPI26_EVENT_DATA_PCIE_ENUMERATION {
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U8 Flags; /*0x00 */
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U8 ReasonCode; /*0x01 */
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U8 PhysicalPort; /*0x02 */
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U8 Reserved1; /*0x03 */
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U32 EnumerationStatus; /*0x04 */
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} MPI26_EVENT_DATA_PCIE_ENUMERATION,
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*PTR_MPI26_EVENT_DATA_PCIE_ENUMERATION,
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Mpi26EventDataPCIeEnumeration_t,
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*pMpi26EventDataPCIeEnumeration_t;
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/*PCIe Enumeration Event data Flags values */
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#define MPI26_EVENT_PCIE_ENUM_DEVICE_CHANGE (0x02)
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#define MPI26_EVENT_PCIE_ENUM_IN_PROGRESS (0x01)
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/*PCIe Enumeration Event data ReasonCode values */
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#define MPI26_EVENT_PCIE_ENUM_RC_STARTED (0x01)
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#define MPI26_EVENT_PCIE_ENUM_RC_COMPLETED (0x02)
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/*PCIe Enumeration Event data EnumerationStatus values */
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#define MPI26_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0x40000000)
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#define MPI26_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0x20000000)
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#define MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0x10000000)
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/*PCIe Topology Change List Event data (MPI v2.6 and later) */
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/*
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*Host code (drivers, BIOS, utilities, etc.) should leave this define set to
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*one and check NumEntries at runtime.
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*/
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#ifndef MPI26_EVENT_PCIE_TOPO_PORT_COUNT
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#define MPI26_EVENT_PCIE_TOPO_PORT_COUNT (1)
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#endif
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typedef struct _MPI26_EVENT_PCIE_TOPO_PORT_ENTRY {
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U16 AttachedDevHandle; /*0x00 */
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U8 PortStatus; /*0x02 */
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U8 Reserved1; /*0x03 */
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U8 CurrentPortInfo; /*0x04 */
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U8 Reserved2; /*0x05 */
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U8 PreviousPortInfo; /*0x06 */
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U8 Reserved3; /*0x07 */
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} MPI26_EVENT_PCIE_TOPO_PORT_ENTRY,
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*PTR_MPI26_EVENT_PCIE_TOPO_PORT_ENTRY,
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Mpi26EventPCIeTopoPortEntry_t,
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*pMpi26EventPCIeTopoPortEntry_t;
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/*PCIe Topology Change List Event data PortStatus values */
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#define MPI26_EVENT_PCIE_TOPO_PS_DEV_ADDED (0x01)
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#define MPI26_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0x02)
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#define MPI26_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0x03)
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#define MPI26_EVENT_PCIE_TOPO_PS_NO_CHANGE (0x04)
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#define MPI26_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05)
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/*PCIe Topology Change List Event data defines for CurrentPortInfo and
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*PreviousPortInfo
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*/
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#define MPI26_EVENT_PCIE_TOPO_PI_LANE_MASK (0xF0)
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#define MPI26_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00)
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#define MPI26_EVENT_PCIE_TOPO_PI_1_LANE (0x10)
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#define MPI26_EVENT_PCIE_TOPO_PI_2_LANES (0x20)
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#define MPI26_EVENT_PCIE_TOPO_PI_4_LANES (0x30)
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#define MPI26_EVENT_PCIE_TOPO_PI_8_LANES (0x40)
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#define MPI26_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0F)
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#define MPI26_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00)
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#define MPI26_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01)
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#define MPI26_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02)
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#define MPI26_EVENT_PCIE_TOPO_PI_RATE_5_0 (0x03)
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#define MPI26_EVENT_PCIE_TOPO_PI_RATE_8_0 (0x04)
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#define MPI26_EVENT_PCIE_TOPO_PI_RATE_16_0 (0x05)
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typedef struct _MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST {
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U16 EnclosureHandle; /*0x00 */
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U16 SwitchDevHandle; /*0x02 */
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U8 NumPorts; /*0x04 */
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U8 Reserved1; /*0x05 */
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U16 Reserved2; /*0x06 */
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U8 NumEntries; /*0x08 */
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U8 StartPortNum; /*0x09 */
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U8 SwitchStatus; /*0x0A */
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U8 PhysicalPort; /*0x0B */
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MPI26_EVENT_PCIE_TOPO_PORT_ENTRY
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PortEntry[MPI26_EVENT_PCIE_TOPO_PORT_COUNT]; /*0x0C */
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} MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST,
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*PTR_MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST,
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Mpi26EventDataPCIeTopologyChangeList_t,
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*pMpi26EventDataPCIeTopologyChangeList_t;
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/*PCIe Topology Change List Event data SwitchStatus values */
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#define MPI26_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0x00)
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#define MPI26_EVENT_PCIE_TOPO_SS_ADDED (0x01)
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#define MPI26_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02)
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#define MPI26_EVENT_PCIE_TOPO_SS_RESPONDING (0x03)
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#define MPI26_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04)
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/*PCIe Link Counter Event data (MPI v2.6 and later) */
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typedef struct _MPI26_EVENT_DATA_PCIE_LINK_COUNTER {
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U64 TimeStamp; /*0x00 */
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U32 Reserved1; /*0x08 */
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U8 LinkEventCode; /*0x0C */
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U8 LinkNum; /*0x0D */
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U16 Reserved2; /*0x0E */
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U32 LinkEventInfo; /*0x10 */
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U8 CounterType; /*0x14 */
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U8 ThresholdWindow; /*0x15 */
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U8 TimeUnits; /*0x16 */
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U8 Reserved3; /*0x17 */
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U32 EventThreshold; /*0x18 */
|
||||
U16 ThresholdFlags; /*0x1C */
|
||||
U16 Reserved4; /*0x1E */
|
||||
} MPI26_EVENT_DATA_PCIE_LINK_COUNTER,
|
||||
*PTR_MPI26_EVENT_DATA_PCIE_LINK_COUNTER,
|
||||
Mpi26EventDataPcieLinkCounter_t, *pMpi26EventDataPcieLinkCounter_t;
|
||||
|
||||
|
||||
/*use MPI26_PCIELINK3_EVTCODE_ values from mpi2_cnfg.h for the LinkEventCode
|
||||
*field
|
||||
*/
|
||||
|
||||
/*use MPI26_PCIELINK3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType
|
||||
*field
|
||||
*/
|
||||
|
||||
/*use MPI26_PCIELINK3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits
|
||||
*field
|
||||
*/
|
||||
|
||||
/*use MPI26_PCIELINK3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags
|
||||
*field
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* EventAck message
|
||||
****************************************************************************/
|
||||
@@ -1190,6 +1436,14 @@ typedef struct _MPI2_FW_DOWNLOAD_REQUEST {
|
||||
#define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A)
|
||||
#define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
|
||||
#define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY (0x0C)
|
||||
#define MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP (0x0D)
|
||||
#define MPI2_FW_DOWNLOAD_ITYPE_SBR (0x0E)
|
||||
#define MPI2_FW_DOWNLOAD_ITYPE_SBR_BACKUP (0x0F)
|
||||
#define MPI2_FW_DOWNLOAD_ITYPE_HIIM (0x10)
|
||||
#define MPI2_FW_DOWNLOAD_ITYPE_HIIA (0x11)
|
||||
#define MPI2_FW_DOWNLOAD_ITYPE_CTLR (0x12)
|
||||
#define MPI2_FW_DOWNLOAD_ITYPE_IMR_FIRMWARE (0x13)
|
||||
#define MPI2_FW_DOWNLOAD_ITYPE_MR_NVDATA (0x14)
|
||||
#define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
|
||||
|
||||
/*MPI v2.0 FWDownload TransactionContext Element */
|
||||
@@ -1276,6 +1530,14 @@ typedef struct _MPI2_FW_UPLOAD_REQUEST {
|
||||
#define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
|
||||
#define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
|
||||
#define MPI2_FW_UPLOAD_ITYPE_CBB_BACKUP (0x0D)
|
||||
#define MPI2_FW_UPLOAD_ITYPE_SBR (0x0E)
|
||||
#define MPI2_FW_UPLOAD_ITYPE_SBR_BACKUP (0x0F)
|
||||
#define MPI2_FW_UPLOAD_ITYPE_HIIM (0x10)
|
||||
#define MPI2_FW_UPLOAD_ITYPE_HIIA (0x11)
|
||||
#define MPI2_FW_UPLOAD_ITYPE_CTLR (0x12)
|
||||
#define MPI2_FW_UPLOAD_ITYPE_IMR_FIRMWARE (0x13)
|
||||
#define MPI2_FW_UPLOAD_ITYPE_MR_NVDATA (0x14)
|
||||
|
||||
|
||||
/*MPI v2.0 FWUpload TransactionContext Element */
|
||||
typedef struct _MPI2_FW_UPLOAD_TCSGE {
|
||||
@@ -1394,10 +1656,13 @@ typedef struct _MPI2_FW_IMAGE_HEADER {
|
||||
#define MPI26_FW_HEADER_SIGNATURE0_ARC_1 (0x00)
|
||||
#define MPI26_FW_HEADER_SIGNATURE0_ARC_2 (0x01)
|
||||
/* legacy (0x5AEAA55A) */
|
||||
#define MPI26_FW_HEADER_SIGNATURE0_ARC_3 (0x02)
|
||||
#define MPI26_FW_HEADER_SIGNATURE0 \
|
||||
(MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_0)
|
||||
#define MPI26_FW_HEADER_SIGNATURE0_3516 \
|
||||
(MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_1)
|
||||
#define MPI26_FW_HEADER_SIGNATURE0_4008 \
|
||||
(MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_3)
|
||||
|
||||
/*Signature1 field */
|
||||
#define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
|
||||
@@ -1541,6 +1806,13 @@ typedef struct _MPI2_FLASH_LAYOUT_DATA {
|
||||
#define MPI2_FLASH_REGION_COMMON_BOOT_BLOCK (0x0A)
|
||||
#define MPI2_FLASH_REGION_INIT (MPI2_FLASH_REGION_COMMON_BOOT_BLOCK)
|
||||
#define MPI2_FLASH_REGION_CBB_BACKUP (0x0D)
|
||||
#define MPI2_FLASH_REGION_SBR (0x0E)
|
||||
#define MPI2_FLASH_REGION_SBR_BACKUP (0x0F)
|
||||
#define MPI2_FLASH_REGION_HIIM (0x10)
|
||||
#define MPI2_FLASH_REGION_HIIA (0x11)
|
||||
#define MPI2_FLASH_REGION_CTLR (0x12)
|
||||
#define MPI2_FLASH_REGION_IMR_FIRMWARE (0x13)
|
||||
#define MPI2_FLASH_REGION_MR_NVDATA (0x14)
|
||||
|
||||
/*ImageRevision */
|
||||
#define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
|
||||
@@ -1825,6 +2097,8 @@ typedef struct _MPI26_IOUNIT_CONTROL_REQUEST {
|
||||
#define MPI26_CTRL_OP_DEV_ENABLE_PERSIST_CONNECTION (0x17)
|
||||
#define MPI26_CTRL_OP_DEV_DISABLE_PERSIST_CONNECTION (0x18)
|
||||
#define MPI26_CTRL_OP_DEV_CLOSE_PERSIST_CONNECTION (0x19)
|
||||
#define MPI26_CTRL_OP_ENABLE_NVME_SGL_FORMAT (0x1A)
|
||||
#define MPI26_CTRL_OP_DISABLE_NVME_SGL_FORMAT (0x1B)
|
||||
#define MPI26_CTRL_OP_PRODUCT_SPECIFIC_MIN (0x80)
|
||||
|
||||
/* values for the PrimFlags field */
|
||||
|
||||
Reference in New Issue
Block a user