drm/radeon/kms: simplify & improve GPU reset V2
This simplify and improve GPU reset for R1XX-R6XX hw, it's not 100% reliable here are result: - R1XX/R2XX works bunch of time in a row, sometimes it seems it can work indifinitly - R3XX/R3XX the most unreliable one, sometimes you will be able to reset few times, sometimes not even once - R5XX more reliable than previous hw, seems to work most of the times but once in a while it fails for no obvious reasons (same status than previous reset just no same happy ending) - R6XX/R7XX are lot more reliable with this patch, still it seems that it can fail after a bunch (reset every 2sec for 3hour bring down the GPU & computer) This have been tested on various hw, for some odd reasons i wasn't able to lockup RS480/RS690 (while they use to love locking up). Note that on R1XX-R5XX the cursor will disapear after lockup haven't checked why, switch to console and back to X will restore cursor. Next step is to record the bogus command that leaded to the lockup. V2 Fix r6xx resume path to avoid reinitializing blit module, use the gpu_lockup boolean to avoid entering inifinite waiting loop on fence while reiniting the GPU Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Jerome Glisse
committed by
Dave Airlie
Dave Airlie
parent
a2d07b7438
commit
90aca4d274
@@ -151,6 +151,10 @@ void rv370_pcie_gart_disable(struct radeon_device *rdev)
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u32 tmp;
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int r;
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WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);
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WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);
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WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
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WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
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tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
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tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
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WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
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@@ -323,7 +327,6 @@ void r300_gpu_init(struct radeon_device *rdev)
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{
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uint32_t gb_tile_config, tmp;
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r100_hdp_reset(rdev);
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/* FIXME: rv380 one pipes ? */
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if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
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(rdev->family == CHIP_R350)) {
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@@ -376,57 +379,6 @@ void r300_gpu_init(struct radeon_device *rdev)
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rdev->num_gb_pipes, rdev->num_z_pipes);
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}
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int r300_ga_reset(struct radeon_device *rdev)
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{
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uint32_t tmp;
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bool reinit_cp;
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int i;
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reinit_cp = rdev->cp.ready;
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rdev->cp.ready = false;
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for (i = 0; i < rdev->usec_timeout; i++) {
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WREG32(RADEON_CP_CSQ_MODE, 0);
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WREG32(RADEON_CP_CSQ_CNTL, 0);
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WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
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(void)RREG32(RADEON_RBBM_SOFT_RESET);
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udelay(200);
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WREG32(RADEON_RBBM_SOFT_RESET, 0);
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/* Wait to prevent race in RBBM_STATUS */
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mdelay(1);
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tmp = RREG32(RADEON_RBBM_STATUS);
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if (tmp & ((1 << 20) | (1 << 26))) {
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DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
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/* GA still busy soft reset it */
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WREG32(0x429C, 0x200);
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WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
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WREG32(R300_RE_SCISSORS_TL, 0);
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WREG32(R300_RE_SCISSORS_BR, 0);
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WREG32(0x24AC, 0);
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}
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/* Wait to prevent race in RBBM_STATUS */
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mdelay(1);
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tmp = RREG32(RADEON_RBBM_STATUS);
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if (!(tmp & ((1 << 20) | (1 << 26)))) {
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break;
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}
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}
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for (i = 0; i < rdev->usec_timeout; i++) {
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tmp = RREG32(RADEON_RBBM_STATUS);
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if (!(tmp & ((1 << 20) | (1 << 26)))) {
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DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
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tmp);
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if (reinit_cp) {
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return r100_cp_init(rdev, rdev->cp.ring_size);
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}
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return 0;
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}
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DRM_UDELAY(1);
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}
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tmp = RREG32(RADEON_RBBM_STATUS);
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DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
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return -1;
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}
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bool r300_gpu_is_lockup(struct radeon_device *rdev)
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{
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u32 rbbm_status;
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@@ -451,37 +403,69 @@ bool r300_gpu_is_lockup(struct radeon_device *rdev)
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int r300_asic_reset(struct radeon_device *rdev)
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{
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uint32_t status;
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struct r100_mc_save save;
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u32 status, tmp;
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/* reset order likely matter */
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status = RREG32(RADEON_RBBM_STATUS);
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r100_mc_stop(rdev, &save);
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status = RREG32(R_000E40_RBBM_STATUS);
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if (!G_000E40_GUI_ACTIVE(status)) {
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return 0;
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}
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status = RREG32(R_000E40_RBBM_STATUS);
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dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
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/* reset HDP */
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r100_hdp_reset(rdev);
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/* reset rb2d */
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if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
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r100_rb2d_reset(rdev);
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}
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/* reset GA */
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if (status & ((1 << 20) | (1 << 26))) {
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r300_ga_reset(rdev);
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}
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/* reset CP */
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status = RREG32(RADEON_RBBM_STATUS);
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if (status & (1 << 16)) {
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r100_cp_reset(rdev);
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}
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/* stop CP */
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WREG32(RADEON_CP_CSQ_CNTL, 0);
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tmp = RREG32(RADEON_CP_RB_CNTL);
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WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
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WREG32(RADEON_CP_RB_RPTR_WR, 0);
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WREG32(RADEON_CP_RB_WPTR, 0);
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WREG32(RADEON_CP_RB_CNTL, tmp);
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/* save PCI state */
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pci_save_state(rdev->pdev);
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/* disable bus mastering */
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r100_bm_disable(rdev);
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WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
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S_0000F0_SOFT_RESET_GA(1));
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RREG32(R_0000F0_RBBM_SOFT_RESET);
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mdelay(500);
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WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
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mdelay(1);
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status = RREG32(R_000E40_RBBM_STATUS);
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dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
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/* resetting the CP seems to be problematic sometimes it end up
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* hard locking the computer, but it's necessary for successfull
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* reset more test & playing is needed on R3XX/R4XX to find a
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* reliable (if any solution)
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*/
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WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
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RREG32(R_0000F0_RBBM_SOFT_RESET);
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mdelay(500);
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WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
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mdelay(1);
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status = RREG32(R_000E40_RBBM_STATUS);
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dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
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/* reset MC */
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WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
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RREG32(R_0000F0_RBBM_SOFT_RESET);
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mdelay(500);
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WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
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mdelay(1);
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status = RREG32(R_000E40_RBBM_STATUS);
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dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
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/* restore PCI & busmastering */
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pci_restore_state(rdev->pdev);
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r100_enable_bm(rdev);
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/* Check if GPU is idle */
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status = RREG32(RADEON_RBBM_STATUS);
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if (status & RADEON_RBBM_ACTIVE) {
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DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
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if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
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dev_err(rdev->dev, "failed to reset GPU\n");
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rdev->gpu_lockup = true;
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return -1;
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}
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DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
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r100_mc_resume(rdev, &save);
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dev_info(rdev->dev, "GPU reset succeed\n");
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return 0;
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}
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/*
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* r300,r350,rv350,rv380 VRAM info
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*/
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