Merge tag 'drm-intel-next-2020-03-13' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
UAPI Changes: On i915 we have a new UAPI to allow userspace to specify CS ring buffer size on construction (I915_CONTEXT_PARAM_RINGSIZE) and also new sysfs entries exposing various engine properties GVT Changes: VFIO edid getting expanded to all platforms and a big cleanup around attr group, unused vblank complete, kvmgt, Intel engine and dev_priv usages. i915 Changes: - new UAPI to allow userspace to specify CS ring buffer size on construction (I915_CONTEXT_PARAM_RINGSIZE) - (Chris) - New sysfs entries exposing various engine properties (Chris) - Tiger Lake is out of require_force_probe protection (Jose) - Changes in many places around active requests, reset and heartbeat (Chris) - Stop assigning drm-dev_private pointer (Jani) - Many code refactor in many places, including intel_modeset_init, increasing use of intel_uncore_*, vgpu, and gvt stuff (Jani) - Fixes around display pipe iterators (Anshuman) - Tigerlake enabling work (Matt Ropper, Matt Atwood, Ville, Lucas, Daniele, Jose, Anusha, Vivek, Swathi, Caz. Kai) - Code clean-up like reducing use of drm/i915_drv.h, removing unused registers, removing garbage warns, and some other code polishing (Jani, Lucas, Ville) - Selftests fixes, improvements and additions (Chris, Dan, Aditya, Matt Auld) - Fix plane possible_crtcs bit mask (Anshuman) - Fixes and cleanup on GLK pre production identification and w/a (Ville) - Fix display orientation on few cases (Hans, Ville) - dbuf clean-up and improvements for slice arrays handling (Ville) - Improvement around min cdclk calculation (Stanislav) - Fixes and refactor around display PLLs (Imre) - Other execlists and perf fixes (Chris) - Documentation fixes (Jani, Chris) - Fix build issue (Anshuman) - Many more fixes around the locking mechanisms (Chris) - Other fixes and debugability info around preemption (Chris, Tvrtko) - Add mechanism to submit a context WA on ring submission (Mika) - Clear all Eu/L3 resitual context (Prathap) - More changes around local memory (Abdiel, Matt, Chris) - Fix RPS (Chris) - DP MST fix (Lyude) - Display FBC fixes (Jose, RK) - debugfs cleanup (Tvrtko) - More convertion towards drm_debive based loggin (Wambui, Ram) - Avoid potential buffer overflow (Takashi) - Ice Lake and Elkhart Lake workarounds (Matt Roper) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200314001535.GA2969344@intel.com
This commit is contained in:
Dave Airlie
@@ -34,7 +34,6 @@
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#include <drm/drm_drv.h>
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#include <drm/drm_irq.h>
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#include <drm/i915_drm.h>
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#include "display/intel_display_types.h"
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#include "display/intel_fifo_underrun.h"
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@@ -169,6 +168,14 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = {
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[HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
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};
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static void
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intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
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{
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struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
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drm_crtc_handle_vblank(&crtc->base);
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}
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void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
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i915_reg_t iir, i915_reg_t ier)
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{
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@@ -1210,8 +1217,8 @@ static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
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u32 crc2, u32 crc3,
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u32 crc4)
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{
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struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
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struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
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struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
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u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 };
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trace_intel_pipe_crc(crtc, crcs);
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@@ -1374,7 +1381,7 @@ static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
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for_each_pipe(dev_priv, pipe) {
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if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
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drm_handle_vblank(&dev_priv->drm, pipe);
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intel_handle_vblank(dev_priv, pipe);
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if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
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i9xx_pipe_crc_irq_handler(dev_priv, pipe);
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@@ -1392,7 +1399,7 @@ static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
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for_each_pipe(dev_priv, pipe) {
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if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
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drm_handle_vblank(&dev_priv->drm, pipe);
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intel_handle_vblank(dev_priv, pipe);
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if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
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blc_event = true;
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@@ -1416,7 +1423,7 @@ static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
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for_each_pipe(dev_priv, pipe) {
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if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
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drm_handle_vblank(&dev_priv->drm, pipe);
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intel_handle_vblank(dev_priv, pipe);
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if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
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blc_event = true;
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@@ -1442,7 +1449,7 @@ static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
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for_each_pipe(dev_priv, pipe) {
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if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
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drm_handle_vblank(&dev_priv->drm, pipe);
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intel_handle_vblank(dev_priv, pipe);
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if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
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i9xx_pipe_crc_irq_handler(dev_priv, pipe);
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@@ -1749,11 +1756,12 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
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if (pch_iir & SDE_POISON)
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drm_err(&dev_priv->drm, "PCH poison interrupt\n");
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if (pch_iir & SDE_FDI_MASK)
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if (pch_iir & SDE_FDI_MASK) {
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for_each_pipe(dev_priv, pipe)
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drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
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pipe_name(pipe),
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I915_READ(FDI_RX_IIR(pipe)));
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}
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if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
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drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n");
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@@ -1833,11 +1841,12 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
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if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
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drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n");
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if (pch_iir & SDE_FDI_MASK_CPT)
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if (pch_iir & SDE_FDI_MASK_CPT) {
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for_each_pipe(dev_priv, pipe)
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drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
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pipe_name(pipe),
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I915_READ(FDI_RX_IIR(pipe)));
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}
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if (pch_iir & SDE_ERROR_CPT)
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cpt_serr_int_handler(dev_priv);
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@@ -1978,7 +1987,7 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
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for_each_pipe(dev_priv, pipe) {
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if (de_iir & DE_PIPE_VBLANK(pipe))
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drm_handle_vblank(&dev_priv->drm, pipe);
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intel_handle_vblank(dev_priv, pipe);
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if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
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intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
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@@ -2031,7 +2040,7 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
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for_each_pipe(dev_priv, pipe) {
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if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
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drm_handle_vblank(&dev_priv->drm, pipe);
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intel_handle_vblank(dev_priv, pipe);
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}
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/* check event from PCH */
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@@ -2344,7 +2353,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
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I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
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if (iir & GEN8_PIPE_VBLANK)
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drm_handle_vblank(&dev_priv->drm, pipe);
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intel_handle_vblank(dev_priv, pipe);
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if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
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hsw_pipe_crc_irq_handler(dev_priv, pipe);
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