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Merge tag 'metag-v3.9-rc1-v4' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/metag

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Pull new ImgTec Meta architecture from James Hogan:
 "This adds core architecture support for Imagination's Meta processor
  cores, followed by some later miscellaneous arch/metag cleanups and
  fixes which I kept separate to ease review:

   - Support for basic Meta 1 (ATP) and Meta 2 (HTP) core architecture
   - A few fixes all over, particularly for symbol prefixes
   - A few privilege protection fixes
   - Several cleanups (setup.c includes, split out a lot of
     metag_ksyms.c)
   - Fix some missing exports
   - Convert hugetlb to use vm_unmapped_area()
   - Copy device tree to non-init memory
   - Provide dma_get_sgtable()"

* tag 'metag-v3.9-rc1-v4' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/metag: (61 commits)
  metag: Provide dma_get_sgtable()
  metag: prom.h: remove declaration of metag_dt_memblock_reserve()
  metag: copy devicetree to non-init memory
  metag: cleanup metag_ksyms.c includes
  metag: move mm/init.c exports out of metag_ksyms.c
  metag: move usercopy.c exports out of metag_ksyms.c
  metag: move setup.c exports out of metag_ksyms.c
  metag: move kick.c exports out of metag_ksyms.c
  metag: move traps.c exports out of metag_ksyms.c
  metag: move irq enable out of irqflags.h on SMP
  genksyms: fix metag symbol prefix on crc symbols
  metag: hugetlb: convert to vm_unmapped_area()
  metag: export clear_page and copy_page
  metag: export metag_code_cache_flush_all
  metag: protect more non-MMU memory regions
  metag: make TXPRIVEXT bits explicit
  metag: kernel/setup.c: sort includes
  perf: Enable building perf tools for Meta
  metag: add boot time LNKGET/LNKSET check
  metag: add __init to metag_cache_probe()
  ...
This commit is contained in:
Linus Torvalds
2013-03-03 12:06:09 -08:00
parent 529e5fbcd8 c60ac31542
commit 8fd5e7a2d9
200 changed files with 26934 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/00-INDEX
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@@ -299,6 +299,8 @@ memory-hotplug.txt
- Hotpluggable memory support, how to use and current status.
memory.txt
- info on typical Linux memory problems.
metag/
- directory with info about Linux on Meta architecture.
mips/
- directory with info about Linux on MIPS architecture.
misc-devices/

82
Documentation/devicetree/bindings/metag/meta-intc.txt Normal file
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@@ -0,0 +1,82 @@
* Meta External Trigger Controller Binding
This binding specifies what properties must be available in the device tree
representation of a Meta external trigger controller.
Required properties:
- compatible: Specifies the compatibility list for the interrupt controller.
The type shall be <string> and the value shall include "img,meta-intc".
- num-banks: Specifies the number of interrupt banks (each of which can
handle 32 interrupt sources).
- interrupt-controller: The presence of this property identifies the node
as an interupt controller. No property value shall be defined.
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source. The type shall be a <u32> and the value shall be 2.
- #address-cells: Specifies the number of cells needed to encode an
address. The type shall be <u32> and the value shall be 0. As such,
'interrupt-map' nodes do not have to specify a parent unit address.
Optional properties:
- no-mask: The controller doesn't have any mask registers.
* Interrupt Specifier Definition
Interrupt specifiers consists of 2 cells encoded as follows:
- <1st-cell>: The interrupt-number that identifies the interrupt source.
- <2nd-cell>: The Linux interrupt flags containing level-sense information,
encoded as follows:
1 = edge triggered
4 = level-sensitive
* Examples
Example 1:
/*
* Meta external trigger block
*/
intc: intc {
// This is an interrupt controller node.
interrupt-controller;
// No address cells so that 'interrupt-map' nodes which
// reference this interrupt controller node do not need a parent
// address specifier.
#address-cells = <0>;
// Two cells to encode interrupt sources.
#interrupt-cells = <2>;
// Number of interrupt banks
num-banks = <2>;
// No HWMASKEXT is available (specify on Chorus2 and Comet ES1)
no-mask;
// Compatible with Meta hardware trigger block.
compatible = "img,meta-intc";
};
Example 2:
/*
* An interrupt generating device that is wired to a Meta external
* trigger block.
*/
uart1: uart@0x02004c00 {
// Interrupt source '5' that is level-sensitive.
// Note that there are only two cells as specified in the
// interrupt parent's '#interrupt-cells' property.
interrupts = <5 4 /* level */>;
// The interrupt controller that this device is wired to.
interrupt-parent = <&intc>;
};

4
Documentation/kernel-parameters.txt
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@@ -978,6 +978,10 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
If specified, z/VM IUCV HVC accepts connections
from listed z/VM user IDs only.
hwthread_map= [METAG] Comma-separated list of Linux cpu id to
hardware thread id mappings.
Format: <cpu>:<hwthread>
keep_bootcon [KNL]
Do not unregister boot console at start. This is only
useful for debugging when something happens in the window

4
Documentation/metag/00-INDEX Normal file
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@@ -0,0 +1,4 @@
00-INDEX
- this file
kernel-ABI.txt
- Documents metag ABI details

256
Documentation/metag/kernel-ABI.txt Normal file
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@@ -0,0 +1,256 @@
==========================
KERNEL ABIS FOR METAG ARCH
==========================
This document describes the Linux ABIs for the metag architecture, and has the
following sections:
(*) Outline of registers
(*) Userland registers
(*) Kernel registers
(*) System call ABI
(*) Calling conventions
====================
OUTLINE OF REGISTERS
====================
The main Meta core registers are arranged in units:
UNIT Type DESCRIPTION GP EXT PRIV GLOBAL
======= ======= =============== ======= ======= ======= =======
CT Special Control unit
D0 General Data unit 0 0-7 8-15 16-31 16-31
D1 General Data unit 1 0-7 8-15 16-31 16-31
A0 General Address unit 0 0-3 4-7 8-15 8-15
A1 General Address unit 1 0-3 4-7 8-15 8-15
PC Special PC unit 0 1
PORT Special Ports
TR Special Trigger unit 0-7
TT Special Trace unit 0-5
FX General FP unit 0-15
GP registers form part of the main context.
Extended context registers (EXT) may not be present on all hardware threads and
can be context switched if support is enabled and the appropriate bits are set
in e.g. the D0.8 register to indicate what extended state to preserve.
Global registers are shared between threads and are privilege protected.
See arch/metag/include/asm/metag_regs.h for definitions relating to core
registers and the fields and bits they contain. See the TRMs for further details
about special registers.
Several special registers are preserved in the main context, these are the
interesting ones:
REG (ALIAS) PURPOSE
======================= ===============================================
CT.1 (TXMODE) Processor mode bits (particularly for DSP)
CT.2 (TXSTATUS) Condition flags and LSM_STEP (MGET/MSET step)
CT.3 (TXRPT) Branch repeat counter
PC.0 (PC) Program counter
Some of the general registers have special purposes in the ABI and therefore
have aliases:
D0 REG (ALIAS) PURPOSE D1 REG (ALIAS) PURPOSE
=============== =============== =============== =======================
D0.0 (D0Re0) 32bit result D1.0 (D1Re0) Top half of 64bit result
D0.1 (D0Ar6) Argument 6 D1.1 (D1Ar5) Argument 5
D0.2 (D0Ar4) Argument 4 D1.2 (D1Ar3) Argument 3
D0.3 (D0Ar2) Argument 2 D1.3 (D1Ar1) Argument 1
D0.4 (D0FrT) Frame temp D1.4 (D1RtP) Return pointer
D0.5 Call preserved D1.5 Call preserved
D0.6 Call preserved D1.6 Call preserved
D0.7 Call preserved D1.7 Call preserved
A0 REG (ALIAS) PURPOSE A1 REG (ALIAS) PURPOSE
=============== =============== =============== =======================
A0.0 (A0StP) Stack pointer A1.0 (A1GbP) Global base pointer
A0.1 (A0FrP) Frame pointer A1.1 (A1LbP) Local base pointer
A0.2 A1.2
A0.3 A1.3
==================
USERLAND REGISTERS
==================
All the general purpose D0, D1, A0, A1 registers are preserved when entering the
kernel (including asynchronous events such as interrupts and timer ticks) except
the following which have special purposes in the ABI:
REGISTERS WHEN STATUS PURPOSE
=============== ======= =============== ===============================
D0.8 DSP Preserved ECH, determines what extended
DSP state to preserve.
A0.0 (A0StP) ALWAYS Preserved Stack >= A0StP may be clobbered
at any time by the creation of a
signal frame.
A1.0 (A1GbP) SMP Clobbered Used as temporary for loading
kernel stack pointer and saving
core context.
A0.15 !SMP Protected Stores kernel stack pointer.
A1.15 ALWAYS Protected Stores kernel base pointer.
On UP A0.15 is used to store the kernel stack pointer for storing the userland
context. A0.15 is global between hardware threads though which means it cannot
be used on SMP for this purpose. Since no protected local registers are
available A1GbP is reserved for use as a temporary to allow a percpu stack
pointer to be loaded for storing the rest of the context.
================
KERNEL REGISTERS
================
When in the kernel the following registers have special purposes in the ABI:
REGISTERS WHEN STATUS PURPOSE
=============== ======= =============== ===============================
A0.0 (A0StP) ALWAYS Preserved Stack >= A0StP may be clobbered
at any time by the creation of
an irq signal frame.
A1.0 (A1GbP) ALWAYS Preserved Reserved (kernel base pointer).
===============
SYSTEM CALL ABI
===============
When a system call is made, the following registers are effective:
REGISTERS CALL RETURN
=============== ======================= ===============================
D0.0 (D0Re0) Return value (or -errno)
D1.0 (D1Re0) System call number Clobbered
D0.1 (D0Ar6) Syscall arg #6 Preserved
D1.1 (D1Ar5) Syscall arg #5 Preserved
D0.2 (D0Ar4) Syscall arg #4 Preserved
D1.2 (D1Ar3) Syscall arg #3 Preserved
D0.3 (D0Ar2) Syscall arg #2 Preserved
D1.3 (D1Ar1) Syscall arg #1 Preserved
Due to the limited number of argument registers and some system calls with badly
aligned 64-bit arguments, 64-bit values are always packed in consecutive
arguments, even if this is contrary to the normal calling conventions (where the
two halves would go in a matching pair of data registers).
For example fadvise64_64 usually has the signature:
long sys_fadvise64_64(i32 fd, i64 offs, i64 len, i32 advice);
But for metag fadvise64_64 is wrapped so that the 64-bit arguments are packed:
long sys_fadvise64_64_metag(i32 fd, i32 offs_lo,
i32 offs_hi, i32 len_lo,
i32 len_hi, i32 advice)
So the arguments are packed in the registers like this:
D0 REG (ALIAS) VALUE D1 REG (ALIAS) VALUE
=============== =============== =============== =======================
D0.1 (D0Ar6) advice D1.1 (D1Ar5) hi(len)
D0.2 (D0Ar4) lo(len) D1.2 (D1Ar3) hi(offs)
D0.3 (D0Ar2) lo(offs) D1.3 (D1Ar1) fd
===================
CALLING CONVENTIONS
===================
These calling conventions apply to both user and kernel code. The stack grows
from low addresses to high addresses in the metag ABI. The stack pointer (A0StP)
should always point to the next free address on the stack and should at all
times be 64-bit aligned. The following registers are effective at the point of a
call:
REGISTERS CALL RETURN
=============== ======================= ===============================
D0.0 (D0Re0) 32bit return value
D1.0 (D1Re0) Upper half of 64bit return value
D0.1 (D0Ar6) 32bit argument #6 Clobbered
D1.1 (D1Ar5) 32bit argument #5 Clobbered
D0.2 (D0Ar4) 32bit argument #4 Clobbered
D1.2 (D1Ar3) 32bit argument #3 Clobbered
D0.3 (D0Ar2) 32bit argument #2 Clobbered
D1.3 (D1Ar1) 32bit argument #1 Clobbered
D0.4 (D0FrT) Clobbered
D1.4 (D1RtP) Return pointer Clobbered
D{0-1}.{5-7} Preserved
A0.0 (A0StP) Stack pointer Preserved
A1.0 (A0GbP) Preserved
A0.1 (A0FrP) Frame pointer Preserved
A1.1 (A0LbP) Preserved
A{0-1},{2-3} Clobbered
64-bit arguments are placed in matching pairs of registers (i.e. the same
register number in both D0 and D1 units), with the least significant half in D0
and the most significant half in D1, leaving a gap where necessary. Futher
arguments are stored on the stack in reverse order (earlier arguments at higher
addresses):
ADDRESS 0 1 2 3 4 5 6 7
=============== ===== ===== ===== ===== ===== ===== ===== =====
A0StP -->
A0StP-0x08 32bit argument #8 32bit argument #7
A0StP-0x10 32bit argument #10 32bit argument #9
Function prologues tend to look a bit like this:
/* If frame pointer in use, move it to frame temp register so it can be
easily pushed onto stack */
MOV D0FrT,A0FrP
/* If frame pointer in use, set it to stack pointer */
ADD A0FrP,A0StP,#0
/* Preserve D0FrT, D1RtP, D{0-1}.{5-7} on stack, incrementing A0StP */
MSETL [A0StP++],D0FrT,D0.5,D0.6,D0.7
/* Allocate some stack space for local variables */
ADD A0StP,A0StP,#0x10
At this point the stack would look like this:
ADDRESS 0 1 2 3 4 5 6 7
=============== ===== ===== ===== ===== ===== ===== ===== =====
A0StP -->
A0StP-0x08
A0StP-0x10
A0StP-0x18 Old D0.7 Old D1.7
A0StP-0x20 Old D0.6 Old D1.6
A0StP-0x28 Old D0.5 Old D1.5
A0FrP --> Old A0FrP (frame ptr) Old D1RtP (return ptr)
A0FrP-0x08 32bit argument #8 32bit argument #7
A0FrP-0x10 32bit argument #10 32bit argument #9
Function epilogues tend to differ depending on the use of a frame pointer. An
example of a frame pointer epilogue:
/* Restore D0FrT, D1RtP, D{0-1}.{5-7} from stack, incrementing A0FrP */
MGETL D0FrT,D0.5,D0.6,D0.7,[A0FrP++]
/* Restore stack pointer to where frame pointer was before increment */
SUB A0StP,A0FrP,#0x20
/* Restore frame pointer from frame temp */
MOV A0FrP,D0FrT
/* Return to caller via restored return pointer */
MOV PC,D1RtP
If the function hasn't touched the frame pointer, MGETL cannot be safely used
with A0StP as it always increments and that would expose the stack to clobbering
by interrupts (kernel) or signals (user). Therefore it's common to see the MGETL
split into separate GETL instructions:
/* Restore D0FrT, D1RtP, D{0-1}.{5-7} from stack */
GETL D0FrT,D1RtP,[A0StP+#-0x30]
GETL D0.5,D1.5,[A0StP+#-0x28]
GETL D0.6,D1.6,[A0StP+#-0x20]
GETL D0.7,D1.7,[A0StP+#-0x18]
/* Restore stack pointer */
SUB A0StP,A0StP,#0x30
/* Return to caller via restored return pointer */
MOV PC,D1RtP