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Merge tag 'mmc-v5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc

Browse Source 
Pull MMC updates from Ulf Hansson:
 "MMC core:

   - Add a new host cap bit and a corresponding DT property, to support
     power cycling of the card by FW at system suspend/resume.

   - Fix clock rate setting for SDIO in SDR12/SDR25 speed-mode

   - Fix switch to 1/4-bit mode at system suspend/resume for SD-combo
     cards

   - Convert the mmc-pwrseq DT bindings to the json-schema

   - Always allow the card detect uevent to be consumed by userspace

  MMC host controllers:

   - Convert a few DT bindings to the json-schema

   - mtk-sd:
      - Add support for command queue through cqhci
      - Add support for the MT6779 variant

   - renesas_sdhi_internal_dmac:
      - Fix dma unmapping in the error path

   - sdhci_am654:
      - Add support for the AM65x PG2.0 variant
      - Extend support for phys/clocks

   - sdhci-cadence:
      - Drop incorrect HW tuning for SD mode

   - sdhci-msm:
      - Add support for interconnect bandwidth scaling
      - Enable internal voltage control
      - Enable low power state for pinctrls

   - sdhci-of-at91:
      - Ludovic Desroches handovers maintenance to Eugen Hristev

   - sdhci-pci-gli:
      - Improve clock handling for GL975x

   - sdhci-pci-o2micro:
      - Add HW tuning for SDR104 mode
      - Fix support for O2 host controller Seabird1"

* tag 'mmc-v5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (66 commits)
  mmc: mediatek: make function msdc_cqe_disable() static
  MAINTAINERS: mmc: sdhci-of-at91: handover maintenance to Eugen Hristev
  dt-bindings: mmc: mediatek: Add document for mt6779
  mmc: mediatek: command queue support
  mmc: mediatek: refine msdc timeout api
  mmc: mediatek: add MT6779 MMC driver support
  mmc: sdhci-pci-o2micro: Add HW tuning for SDR104 mode
  mmc: sdhci-pci-o2micro: Bug fix for O2 host controller Seabird1
  mmc: via-sdmmc: use generic power management
  memstick: jmb38x_ms: use generic power management
  mmc: sdhci-cadence: do not use hardware tuning for SD mode
  mmc: sdhci-pci-gli: Set SDR104's clock to 205MHz and enable SSC for GL975x
  mmc: cqhci: Fix a print format for the task descriptor
  mmc: sdhci-of-arasan: fix timings allocation code
  mmc: sdhci: Fix a potential uninitialized variable
  dt-bindings: mmc: renesas,sdhi: convert to YAML
  dt-bindings: mmc: convert arasan sdhci bindings to yaml
  mmc: sdhci: Fix potential null pointer access while accessing vqmmc
  mmc: core: Add MMC_CAP2_FULL_PWR_CYCLE_IN_SUSPEND
  dt-bindings: mmc: Add full-pwr-cycle-in-suspend property
  ...
This commit is contained in:
Linus Torvalds
2020-08-05 13:23:24 -07:00
parent 9aebd3254c 7f4bc2e868
commit 8f7be62915
56 changed files with 1671 additions and 643 deletions
Download Patch File Download Diff File Expand all files Collapse all files

192
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
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@@ -1,192 +0,0 @@
Device Tree Bindings for the Arasan SDHCI Controller
The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
Only deviations are documented here.
[1] Documentation/devicetree/bindings/mmc/mmc.txt
[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
[3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
[4] Documentation/devicetree/bindings/phy/phy-bindings.txt
Required Properties:
- compatible: Compatibility string. One of:
- "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
- "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
- "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
- "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
For this device it is strongly suggested to include arasan,soc-ctl-syscon.
- "xlnx,zynqmp-8.9a": ZynqMP SDHCI 8.9a PHY
For this device it is strongly suggested to include clock-output-names and
#clock-cells.
- "xlnx,versal-8.9a": Versal SDHCI 8.9a PHY
For this device it is strongly suggested to include clock-output-names and
#clock-cells.
- "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY
Note: This binding has been deprecated and moved to [5].
- "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY
For this device it is strongly suggested to include arasan,soc-ctl-syscon.
- "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1": Intel LGM SDXC PHY
For this device it is strongly suggested to include arasan,soc-ctl-syscon.
- "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel Keem Bay eMMC
For this device it is strongly suggested to include arasan,soc-ctl-syscon.
- "intel,keembay-sdhci-5.1-sd": Intel Keem Bay SD controller
For this device it is strongly suggested to include arasan,soc-ctl-syscon.
- "intel,keembay-sdhci-5.1-sdio": Intel Keem Bay SDIO controller
For this device it is strongly suggested to include arasan,soc-ctl-syscon.
[5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt
- reg: From mmc bindings: Register location and length.
- clocks: From clock bindings: Handles to clock inputs.
- clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
- interrupts: Interrupt specifier
Required Properties for "arasan,sdhci-5.1":
- phys: From PHY bindings: Phandle for the Generic PHY for arasan.
- phy-names: MUST be "phy_arasan".
Optional Properties:
- arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt)
used to access core corecfg registers. Offsets of registers in this
syscon are determined based on the main compatible string for the device.
- clock-output-names: If specified, this will be the name of the card clock
which will be exposed by this device. Required if #clock-cells is
specified.
- #clock-cells: If specified this should be the value <0> or <1>. With this
property in place we will export one or two clocks representing the Card
Clock. These clocks are expected to be consumed by our PHY.
- xlnx,fails-without-test-cd: when present, the controller doesn't work when
the CD line is not connected properly, and the line is not connected
properly. Test mode can be used to force the controller to function.
- xlnx,int-clock-stable-broken: when present, the controller always reports
that the internal clock is stable even when it is not.
- xlnx,mio-bank: When specified, this will indicate the MIO bank number in
which the command and data lines are configured. If not specified, driver
will assume this as 0.
Example:
sdhci@e0100000 {
compatible = "arasan,sdhci-8.9a";
reg = <0xe0100000 0x1000>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&clkc 21>, <&clkc 32>;
interrupt-parent = <&gic>;
interrupts = <0 24 4>;
} ;
sdhci@e2800000 {
compatible = "arasan,sdhci-5.1";
reg = <0xe2800000 0x1000>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&cru 8>, <&cru 18>;
interrupt-parent = <&gic>;
interrupts = <0 24 4>;
phys = <&emmc_phy>;
phy-names = "phy_arasan";
} ;
sdhci: sdhci@fe330000 {
compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
reg = <0x0 0xfe330000 0x0 0x10000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
clock-names = "clk_xin", "clk_ahb";
arasan,soc-ctl-syscon = <&grf>;
assigned-clocks = <&cru SCLK_EMMC>;
assigned-clock-rates = <200000000>;
clock-output-names = "emmc_cardclock";
phys = <&emmc_phy>;
phy-names = "phy_arasan";
#clock-cells = <0>;
};
sdhci: mmc@ff160000 {
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
interrupt-parent = <&gic>;
interrupts = <0 48 4>;
reg = <0x0 0xff160000 0x0 0x1000>;
clocks = <&clk200>, <&clk200>;
clock-names = "clk_xin", "clk_ahb";
clock-output-names = "clk_out_sd0", "clk_in_sd0";
#clock-cells = <1>;
clk-phase-sd-hs = <63>, <72>;
};
sdhci: mmc@f1040000 {
compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
interrupt-parent = <&gic>;
interrupts = <0 126 4>;
reg = <0x0 0xf1040000 0x0 0x10000>;
clocks = <&clk200>, <&clk200>;
clock-names = "clk_xin", "clk_ahb";
clock-output-names = "clk_out_sd0", "clk_in_sd0";
#clock-cells = <1>;
clk-phase-sd-hs = <132>, <60>;
};
emmc: sdhci@ec700000 {
compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
reg = <0xec700000 0x300>;
interrupt-parent = <&ioapic1>;
interrupts = <44 1>;
clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
<&cgu0 LGM_GCLK_EMMC>;
clock-names = "clk_xin", "clk_ahb", "gate";
clock-output-names = "emmc_cardclock";
#clock-cells = <0>;
phys = <&emmc_phy>;
phy-names = "phy_arasan";
arasan,soc-ctl-syscon = <&sysconf>;
};
sdxc: sdhci@ec600000 {
compatible = "arasan,sdhci-5.1", "intel,lgm-sdhci-5.1-sdxc";
reg = <0xec600000 0x300>;
interrupt-parent = <&ioapic1>;
interrupts = <43 1>;
clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
<&cgu0 LGM_GCLK_SDXC>;
clock-names = "clk_xin", "clk_ahb", "gate";
clock-output-names = "sdxc_cardclock";
#clock-cells = <0>;
phys = <&sdxc_phy>;
phy-names = "phy_arasan";
arasan,soc-ctl-syscon = <&sysconf>;
};
mmc: mmc@33000000 {
compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x33000000 0x0 0x300>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
<&scmi_clk KEEM_BAY_PSS_EMMC>;
phys = <&emmc_phy>;
phy-names = "phy_arasan";
assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
assigned-clock-rates = <200000000>;
clock-output-names = "emmc_cardclock";
#clock-cells = <0>;
arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
};
sd0: mmc@31000000 {
compatible = "intel,keembay-sdhci-5.1-sd";
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x31000000 0x0 0x300>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
<&scmi_clk KEEM_BAY_PSS_SD0>;
arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
};
sd1: mmc@32000000 {
compatible = "intel,keembay-sdhci-5.1-sdio";
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x32000000 0x0 0x300>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD1>,
<&scmi_clk KEEM_BAY_PSS_SD1>;
arasan,soc-ctl-syscon = <&sd1_phy_syscon>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Device Tree Bindings for the Arasan SDHCI Controller
maintainers:
- Adrian Hunter <adrian.hunter@intel.com>
allOf:
- $ref: "mmc-controller.yaml#"
- if:
properties:
compatible:
contains:
const: arasan,sdhci-5.1
then:
required:
- phys
- phy-names
- if:
properties:
compatible:
contains:
enum:
- xlnx,zynqmp-8.9a
- xlnx,versal-8.9a
then:
properties:
clock-output-names:
items:
- const: clk_out_sd0
- const: clk_in_sd0
properties:
compatible:
oneOf:
- const: arasan,sdhci-8.9a # generic Arasan SDHCI 8.9a PHY
- const: arasan,sdhci-4.9a # generic Arasan SDHCI 4.9a PHY
- const: arasan,sdhci-5.1 # generic Arasan SDHCI 5.1 PHY
- items:
- const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY
- const: arasan,sdhci-5.1
description:
For this device it is strongly suggested to include
arasan,soc-ctl-syscon.
- items:
- const: xlnx,zynqmp-8.9a # ZynqMP SDHCI 8.9a PHY
- const: arasan,sdhci-8.9a
description:
For this device it is strongly suggested to include
clock-output-names and '#clock-cells'.
- items:
- const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY
- const: arasan,sdhci-8.9a
description:
For this device it is strongly suggested to include
clock-output-names and '#clock-cells'.
- items:
- const: intel,lgm-sdhci-5.1-emmc # Intel LGM eMMC PHY
- const: arasan,sdhci-5.1
description:
For this device it is strongly suggested to include
arasan,soc-ctl-syscon.
- items:
- const: intel,lgm-sdhci-5.1-sdxc # Intel LGM SDXC PHY
- const: arasan,sdhci-5.1
description:
For this device it is strongly suggested to include
arasan,soc-ctl-syscon.
- items:
- const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
- const: arasan,sdhci-5.1
description:
For this device it is strongly suggested to include
arasan,soc-ctl-syscon.
- const: intel,keembay-sdhci-5.1-sd # Intel Keem Bay SD controller
description:
For this device it is strongly suggested to include
arasan,soc-ctl-syscon.
- const: intel,keembay-sdhci-5.1-sdio # Intel Keem Bay SDIO controller
description:
For this device it is strongly suggested to include
arasan,soc-ctl-syscon.
reg:
maxItems: 1
clocks:
minItems: 2
maxItems: 3
clock-names:
minItems: 2
items:
- const: clk_xin
- const: clk_ahb
- const: gate
interrupts:
maxItems: 1
phys:
maxItems: 1
phy-names:
const: phy_arasan
arasan,soc-ctl-syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description:
A phandle to a syscon device (see ../mfd/syscon.txt) used to access
core corecfg registers. Offsets of registers in this syscon are
determined based on the main compatible string for the device.
clock-output-names:
minItems: 1
maxItems: 2
description:
Name of the card clock which will be exposed by this device.
'#clock-cells':
enum: [0, 1]
description:
With this property in place we will export one or two clocks
representing the Card Clock. These clocks are expected to be
consumed by our PHY.
xlnx,fails-without-test-cd:
$ref: /schemas/types.yaml#/definitions/flag
description:
When present, the controller doesn't work when the CD line is not
connected properly, and the line is not connected properly.
Test mode can be used to force the controller to function.
xlnx,int-clock-stable-broken:
$ref: /schemas/types.yaml#/definitions/flag
description:
When present, the controller always reports that the internal clock
is stable even when it is not.
xlnx,mio-bank:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 2]
default: 0
description:
The MIO bank number in which the command and data lines are configured.
dependencies:
clock-output-names: [ '#clock-cells' ]
'#clock-cells': [ clock-output-names ]
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
mmc@e0100000 {
compatible = "arasan,sdhci-8.9a";
reg = <0xe0100000 0x1000>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&clkc 21>, <&clkc 32>;
interrupt-parent = <&gic>;
interrupts = <0 24 4>;
};
- |
mmc@e2800000 {
compatible = "arasan,sdhci-5.1";
reg = <0xe2800000 0x1000>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&cru 8>, <&cru 18>;
interrupt-parent = <&gic>;
interrupts = <0 24 4>;
phys = <&emmc_phy>;
phy-names = "phy_arasan";
};
- |
#include <dt-bindings/clock/rk3399-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
mmc@fe330000 {
compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
reg = <0xfe330000 0x10000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
clock-names = "clk_xin", "clk_ahb";
arasan,soc-ctl-syscon = <&grf>;
assigned-clocks = <&cru SCLK_EMMC>;
assigned-clock-rates = <200000000>;
clock-output-names = "emmc_cardclock";
phys = <&emmc_phy>;
phy-names = "phy_arasan";
#clock-cells = <0>;
};
- |
mmc@ff160000 {
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
interrupt-parent = <&gic>;
interrupts = <0 48 4>;
reg = <0xff160000 0x1000>;
clocks = <&clk200>, <&clk200>;
clock-names = "clk_xin", "clk_ahb";
clock-output-names = "clk_out_sd0", "clk_in_sd0";
#clock-cells = <1>;
clk-phase-sd-hs = <63>, <72>;
};
- |
mmc@f1040000 {
compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
interrupt-parent = <&gic>;
interrupts = <0 126 4>;
reg = <0xf1040000 0x10000>;
clocks = <&clk200>, <&clk200>;
clock-names = "clk_xin", "clk_ahb";
clock-output-names = "clk_out_sd0", "clk_in_sd0";
#clock-cells = <1>;
clk-phase-sd-hs = <132>, <60>;
};
- |
#define LGM_CLK_EMMC5
#define LGM_CLK_NGI
#define LGM_GCLK_EMMC
mmc@ec700000 {
compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
reg = <0xec700000 0x300>;
interrupt-parent = <&ioapic1>;
interrupts = <44 1>;
clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
<&cgu0 LGM_GCLK_EMMC>;
clock-names = "clk_xin", "clk_ahb", "gate";
clock-output-names = "emmc_cardclock";
#clock-cells = <0>;
phys = <&emmc_phy>;
phy-names = "phy_arasan";
arasan,soc-ctl-syscon = <&sysconf>;
};
- |
#define LGM_CLK_SDIO
#define LGM_GCLK_SDXC
mmc@ec600000 {
compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
reg = <0xec600000 0x300>;
interrupt-parent = <&ioapic1>;
interrupts = <43 1>;
clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
<&cgu0 LGM_GCLK_SDXC>;
clock-names = "clk_xin", "clk_ahb", "gate";
clock-output-names = "sdxc_cardclock";
#clock-cells = <0>;
phys = <&sdxc_phy>;
phy-names = "phy_arasan";
arasan,soc-ctl-syscon = <&sysconf>;
};
- |
#define KEEM_BAY_PSS_AUX_EMMC
#define KEEM_BAY_PSS_EMMC
mmc@33000000 {
compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x33000000 0x300>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
<&scmi_clk KEEM_BAY_PSS_EMMC>;
phys = <&emmc_phy>;
phy-names = "phy_arasan";
assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
assigned-clock-rates = <200000000>;
clock-output-names = "emmc_cardclock";
#clock-cells = <0>;
arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
};
- |
#define KEEM_BAY_PSS_AUX_SD0
#define KEEM_BAY_PSS_SD0
mmc@31000000 {
compatible = "intel,keembay-sdhci-5.1-sd";
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x31000000 0x300>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
<&scmi_clk KEEM_BAY_PSS_SD0>;
arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
};

5
Documentation/devicetree/bindings/mmc/mmc-controller.yaml
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@@ -169,6 +169,11 @@ properties:
description:
Full power cycle of the card is supported.
full-pwr-cycle-in-suspend:
$ref: /schemas/types.yaml#/definitions/flag
description:
Full power cycle of the card in suspend is supported.
mmc-ddr-1_2v:
$ref: /schemas/types.yaml#/definitions/flag
description:

25
Documentation/devicetree/bindings/mmc/mmc-pwrseq-emmc.txt
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@@ -1,25 +0,0 @@
* The simple eMMC hardware reset provider
The purpose of this driver is to perform standard eMMC hw reset
procedure, as described by Jedec 4.4 specification. This procedure is
performed just after MMC core enabled power to the given mmc host (to
fix possible issues if bootloader has left eMMC card in initialized or
unknown state), and before performing complete system reboot (also in
case of emergency reboot call). The latter is needed on boards, which
doesn't have hardware reset logic connected to emmc card and (limited or
broken) ROM bootloaders are unable to read second stage from the emmc
card if the card is left in unknown or already initialized state.
Required properties:
- compatible : contains "mmc-pwrseq-emmc".
- reset-gpios : contains a GPIO specifier. The reset GPIO is asserted
and then deasserted to perform eMMC card reset. To perform
reset procedure as described in Jedec 4.4 specification, the
gpio line should be defined as GPIO_ACTIVE_LOW.
Example:
sdhci0_pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
}

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Documentation/devicetree/bindings/mmc/mmc-pwrseq-emmc.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/mmc-pwrseq-emmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Simple eMMC hardware reset provider binding
maintainers:
- Ulf Hansson <ulf.hansson@linaro.org>
description:
The purpose of this driver is to perform standard eMMC hw reset
procedure, as described by Jedec 4.4 specification. This procedure is
performed just after MMC core enabled power to the given mmc host (to
fix possible issues if bootloader has left eMMC card in initialized or
unknown state), and before performing complete system reboot (also in
case of emergency reboot call). The latter is needed on boards, which
doesn't have hardware reset logic connected to emmc card and (limited or
broken) ROM bootloaders are unable to read second stage from the emmc
card if the card is left in unknown or already initialized state.
properties:
compatible:
const: mmc-pwrseq-emmc
reset-gpios:
minItems: 1
description:
contains a GPIO specifier. The reset GPIO is asserted
and then deasserted to perform eMMC card reset. To perform
reset procedure as described in Jedec 4.4 specification, the
gpio line should be defined as GPIO_ACTIVE_LOW.
required:
- compatible
- reset-gpios
examples:
- |
#include <dt-bindings/gpio/gpio.h>
sdhci0_pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
};
...

16
Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.txt
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@@ -1,16 +0,0 @@
* Marvell SD8787 power sequence provider
Required properties:
- compatible: must be "mmc-pwrseq-sd8787".
- powerdown-gpios: contains a power down GPIO specifier with the
default active state
- reset-gpios: contains a reset GPIO specifier with the default
active state
Example:
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-sd8787";
powerdown-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
reset-gpios = <&twl_gpio 1 GPIO_ACTIVE_LOW>;
}

39
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@@ -0,0 +1,39 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/mmc-pwrseq-sd8787.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell SD8787 power sequence provider binding
maintainers:
- Ulf Hansson <ulf.hansson@linaro.org>
properties:
compatible:
const: mmc-pwrseq-sd8787
powerdown-gpios:
minItems: 1
description:
contains a power down GPIO specifier with the default active state
reset-gpios:
minItems: 1
description:
contains a reset GPIO specifier with the default active state
required:
- compatible
- powerdown-gpios
- reset-gpios
examples:
- |
#include <dt-bindings/gpio/gpio.h>
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-sd8787";
powerdown-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
reset-gpios = <&twl_gpio 1 GPIO_ACTIVE_LOW>;
};
...

31
Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt
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@@ -1,31 +0,0 @@
* The simple MMC power sequence provider
The purpose of the simple MMC power sequence provider is to supports a set of
common properties between various SOC designs. It thus enables us to use the
same provider for several SOC designs.
Required properties:
- compatible : contains "mmc-pwrseq-simple".
Optional properties:
- reset-gpios : contains a list of GPIO specifiers. The reset GPIOs are asserted
at initialization and prior we start the power up procedure of the card.
They will be de-asserted right after the power has been provided to the
card.
- clocks : Must contain an entry for the entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names : Must include the following entry:
"ext_clock" (External clock provided to the card).
- post-power-on-delay-ms : Delay in ms after powering the card and
de-asserting the reset-gpios (if any)
- power-off-delay-us : Delay in us after asserting the reset-gpios (if any)
during power off of the card.
Example:
sdhci0_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
clocks = <&clk_32768_ck>;
clock-names = "ext_clock";
}

62
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@@ -0,0 +1,62 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Simple MMC power sequence provider binding
maintainers:
- Ulf Hansson <ulf.hansson@linaro.org>
description:
The purpose of the simple MMC power sequence provider is to supports a set
of common properties between various SOC designs. It thus enables us to use
the same provider for several SOC designs.
properties:
compatible:
const: mmc-pwrseq-simple
reset-gpios:
minItems: 1
description:
contains a list of GPIO specifiers. The reset GPIOs are asserted
at initialization and prior we start the power up procedure of the card.
They will be de-asserted right after the power has been provided to the
card.
clocks:
minItems: 1
description: Handle for the entry in clock-names.
clock-names:
items:
- const: ext_clock
description: External clock provided to the card.
post-power-on-delay-ms:
description:
Delay in ms after powering the card and de-asserting the
reset-gpios (if any).
$ref: /schemas/types.yaml#/definitions/uint32
power-off-delay-us:
description:
Delay in us after asserting the reset-gpios (if any)
during power off of the card.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- compatible
examples:
- |
#include <dt-bindings/gpio/gpio.h>
sdhci0_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
clocks = <&clk_32768_ck>;
clock-names = "ext_clock";
};
...

1
Documentation/devicetree/bindings/mmc/mtk-sd.txt
View File

@@ -12,6 +12,7 @@ Required properties:
"mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
"mediatek,mt8183-mmc": for mmc host ip compatible with mt8183
"mediatek,mt8516-mmc": for mmc host ip compatible with mt8516
"mediatek,mt6779-mmc": for mmc host ip compatible with mt6779
"mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
"mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
"mediatek,mt7622-mmc": for MT7622 SoC

114
Documentation/devicetree/bindings/mmc/renesas,sdhi.txt
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@@ -1,114 +0,0 @@
* Renesas SDHI SD/MMC controller
Required properties:
- compatible: should contain one or more of the following:
"renesas,sdhi-sh73a0" - SDHI IP on SH73A0 SoC
"renesas,sdhi-r7s72100" - SDHI IP on R7S72100 SoC
"renesas,sdhi-r7s9210" - SDHI IP on R7S9210 SoC
"renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC
"renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC
"renesas,sdhi-r8a7742" - SDHI IP on R8A7742 SoC
"renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC
"renesas,sdhi-r8a7744" - SDHI IP on R8A7744 SoC
"renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC
"renesas,sdhi-r8a774a1" - SDHI IP on R8A774A1 SoC
"renesas,sdhi-r8a774b1" - SDHI IP on R8A774B1 SoC
"renesas,sdhi-r8a774c0" - SDHI IP on R8A774C0 SoC
"renesas,sdhi-r8a77470" - SDHI IP on R8A77470 SoC
"renesas,sdhi-mmc-r8a77470" - SDHI/MMC IP on R8A77470 SoC
"renesas,sdhi-r8a7778" - SDHI IP on R8A7778 SoC
"renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC
"renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC
"renesas,sdhi-r8a7791" - SDHI IP on R8A7791 SoC
"renesas,sdhi-r8a7792" - SDHI IP on R8A7792 SoC
"renesas,sdhi-r8a7793" - SDHI IP on R8A7793 SoC
"renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC
"renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC
"renesas,sdhi-r8a7796" - SDHI IP on R8A77960 SoC
"renesas,sdhi-r8a77961" - SDHI IP on R8A77961 SoC
"renesas,sdhi-r8a77965" - SDHI IP on R8A77965 SoC
"renesas,sdhi-r8a77970" - SDHI IP on R8A77970 SoC
"renesas,sdhi-r8a77980" - SDHI IP on R8A77980 SoC
"renesas,sdhi-r8a77990" - SDHI IP on R8A77990 SoC
"renesas,sdhi-r8a77995" - SDHI IP on R8A77995 SoC
"renesas,sdhi-shmobile" - a generic sh-mobile SDHI controller
"renesas,rcar-gen1-sdhi" - a generic R-Car Gen1 SDHI controller
"renesas,rcar-gen2-sdhi" - a generic R-Car Gen2 and RZ/G1 SDHI
(not SDHI/MMC) controller
"renesas,rcar-gen3-sdhi" - a generic R-Car Gen3 or RZ/G2
SDHI controller
When compatible with the generic version, nodes must list
the SoC-specific version corresponding to the platform
first followed by the generic version.
- clocks: Most controllers only have 1 clock source per channel. However, on
some variations of this controller, the internal card detection
logic that exists in this controller is sectioned off to be run by a
separate second clock source to allow the main core clock to be turned
off to save power.
If 2 clocks are specified by the hardware, you must name them as
"core" and "cd". If the controller only has 1 clock, naming is not
required.
Devices which have more than 1 clock are listed below:
2: R7S72100, R7S9210
Optional properties:
- pinctrl-names: should be "default", "state_uhs"
- pinctrl-0: should contain default/high speed pin ctrl
- pinctrl-1: should contain uhs mode pin ctrl
Example: R8A7790 (R-Car H2) SDHI controller nodes
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
<&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <195000000>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 314>;
};
sdhi1: sd@ee120000 {
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
reg = <0 0xee120000 0 0x328>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
<&dmac1 0xc9>, <&dmac1 0xca>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <195000000>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 313>;
};
sdhi2: sd@ee140000 {
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
<&dmac1 0xc1>, <&dmac1 0xc2>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <97500000>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 312>;
};
sdhi3: sd@ee160000 {
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
<&dmac1 0xd3>, <&dmac1 0xd4>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <97500000>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 311>;
};

191
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@@ -0,0 +1,191 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mmc/renesas,sdhi.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Renesas SDHI SD/MMC controller
maintainers:
- Wolfram Sang <wsa+renesas@sang-engineering.com>
allOf:
- $ref: "mmc-controller.yaml"
properties:
compatible:
oneOf:
- items:
- const: renesas,sdhi-sh73a0 # R-Mobile APE6
- items:
- const: renesas,sdhi-r7s72100 # RZ/A1H
- items:
- const: renesas,sdhi-r7s9210 # SH-Mobile AG5
- items:
- const: renesas,sdhi-r8a73a4 # R-Mobile APE6
- items:
- const: renesas,sdhi-r8a7740 # R-Mobile A1
- items:
- enum:
- renesas,sdhi-r8a7778 # R-Car M1
- renesas,sdhi-r8a7779 # R-Car H1
- const: renesas,rcar-gen1-sdhi # R-Car Gen1
- items:
- enum:
- renesas,sdhi-r8a7742 # RZ/G1H
- renesas,sdhi-r8a7743 # RZ/G1M
- renesas,sdhi-r8a7744 # RZ/G1N
- renesas,sdhi-r8a7745 # RZ/G1E
- renesas,sdhi-r8a77470 # RZ/G1C
- renesas,sdhi-r8a7790 # R-Car H2
- renesas,sdhi-r8a7791 # R-Car M2-W
- renesas,sdhi-r8a7792 # R-Car V2H
- renesas,sdhi-r8a7793 # R-Car M2-N
- renesas,sdhi-r8a7794 # R-Car E2
- const: renesas,rcar-gen2-sdhi # R-Car Gen2 and RZ/G1
- items:
- const: renesas,sdhi-mmc-r8a77470 # RZ/G1C (SDHI/MMC IP)
- items:
- enum:
- renesas,sdhi-r8a774a1 # RZ/G2M
- renesas,sdhi-r8a774b1 # RZ/G2N
- renesas,sdhi-r8a774c0 # RZ/G2E
- renesas,sdhi-r8a7795 # R-Car H3
- renesas,sdhi-r8a7796 # R-Car M3-W
- renesas,sdhi-r8a77961 # R-Car M3-W+
- renesas,sdhi-r8a77965 # R-Car M3-N
- renesas,sdhi-r8a77970 # R-Car V3M
- renesas,sdhi-r8a77980 # R-Car V3H
- renesas,sdhi-r8a77990 # R-Car E3
- renesas,sdhi-r8a77995 # R-Car D3
- const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 3
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
maxItems: 2
items:
- const: core
- const: cd
dmas:
minItems: 4
maxItems: 4
dma-names:
minItems: 4
maxItems: 4
items:
enum:
- tx
- rx
power-domains:
maxItems: 1
resets:
maxItems: 1
pinctrl-0:
minItems: 1
maxItems: 2
pinctrl-1:
maxItems: 1
pinctrl-names:
minItems: 1
maxItems: 2
items:
- const: default
- const: state_uhs
max-frequency: true
required:
- compatible
- reg
- interrupts
- clocks
- power-domains
if:
properties:
compatible:
items:
enum:
- renesas,sdhi-r7s72100
- renesas,sdhi-r7s9210
then:
required:
- clock-names
description:
The internal card detection logic that exists in these controllers is
sectioned off to be run by a separate second clock source to allow
the main core clock to be turned off to save power.
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7790-sysc.h>
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
reg = <0xee100000 0x328>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <195000000>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 314>;
};
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
reg = <0xee120000 0x328>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <195000000>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 313>;
};
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
reg = <0xee140000 0x100>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <97500000>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 312>;
};
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
reg = <0xee160000 0x100>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <97500000>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 311>;
};

1
Documentation/devicetree/bindings/mmc/sdhci-am654.txt
View File

@@ -39,6 +39,7 @@ Optional Properties (Required for ti,am654-sdhci-5.1 and ti,j721e-sdhci-8bit):
Valid values are 33, 40, 50, 66 and 100 ohms.
Optional Properties:
- ti,strobe-sel: strobe select delay for HS400 speed mode. Default value: 0x0.
- ti,clkbuf-sel: Clock Delay Buffer Select
Example:

18
Documentation/devicetree/bindings/mmc/sdhci-msm.txt
View File

@@ -54,6 +54,21 @@ Required properties:
- qcom,dll-config: Chipset and Platform specific value. Use this field to
specify the DLL_CONFIG register value as per Hardware Programming Guide.
Optional Properties:
* Following bus parameters are required for interconnect bandwidth scaling:
- interconnects: Pairs of phandles and interconnect provider specifier
to denote the edge source and destination ports of
the interconnect path.
- interconnect-names: For sdhc, we have two main paths.
1. Data path : sdhc to ddr
2. Config path : cpu to sdhc
For Data interconnect path the name supposed to be
is "sdhc-ddr" and for config interconnect path it is
"cpu-sdhc".
Please refer to Documentation/devicetree/bindings/
interconnect/ for more details.
Example:
sdhc_1: sdhci@f9824900 {
@@ -71,6 +86,9 @@ Example:
clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
clock-names = "core", "iface";
interconnects = <&qnoc MASTER_SDCC_ID &qnoc SLAVE_DDR_ID>,
<&qnoc MASTER_CPU_ID &qnoc SLAVE_SDCC_ID>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
qcom,dll-config = <0x000f642c>;
qcom,ddr-config = <0x80040868>;