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arm64/mm: Correct the cache line size warning with non coherent device

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If the cache line size is greater than ARCH_DMA_MINALIGN (128),
the warning shows and it's tainted as TAINT_CPU_OUT_OF_SPEC.

However, it's not good because as discussed in the thread [1], the cpu
cache line size will be problem only on non-coherent devices.

Since the coherent flag is already introduced to struct device,
show the warning only if the device is non-coherent device and
ARCH_DMA_MINALIGN is smaller than the cpu cache size.

[1] https://lore.kernel.org/linux-arm-kernel/20180514145703.celnlobzn3uh5tc2@localhost/

Signed-off-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Reviewed-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Tested-by: Zhang Lei <zhang.lei@jp.fujitsu.com>
[catalin.marinas@arm.com: removed 'if' block for WARN_TAINT]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Masayoshi Mizuma
2019-06-14 09:11:41 -04:00
committed by Catalin Marinas
parent 1a2a66db49
commit 8f5c9037a5
3 changed files with 16 additions and 7 deletions
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4
arch/arm64/kernel/cacheinfo.c
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@@ -30,12 +30,10 @@
int cache_line_size(void)
{
u32 cwg = cache_type_cwg();
if (coherency_max_size != 0)
return coherency_max_size;
return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
return cache_line_size_of_cpu();
}
EXPORT_SYMBOL_GPL(cache_line_size);