Merge tag 'for-linus-20160324' of git://git.infradead.org/linux-mtd
Pull MTD updates from Brian Norris: "NAND: - Add sunxi_nand randomizer support - begin refactoring NAND ecclayout structs - fix pxa3xx_nand dmaengine usage - brcmnand: fix support for v7.1 controller - add Qualcomm NAND controller driver SPI NOR: - add new ls1021a, ls2080a support to Freescale QuadSPI - add new flash ID entries - support bottom-block protection for Winbond flash - support Status Register Write Protect - remove broken QPI support for Micron SPI flash JFFS2: - improve post-mount CRC scan efficiency General: - refactor bcm63xxpart parser, to later extend for NAND - add writebuf size parameter to mtdram Other minor code quality improvements" * tag 'for-linus-20160324' of git://git.infradead.org/linux-mtd: (72 commits) mtd: nand: remove kerneldoc for removed function parameter mtd: nand: Qualcomm NAND controller driver dt/bindings: qcom_nandc: Add DT bindings mtd: nand: don't select chip in nand_chip's block_bad op mtd: spi-nor: support lock/unlock for a few Winbond chips mtd: spi-nor: add TB (Top/Bottom) protect support mtd: spi-nor: add SPI_NOR_HAS_LOCK flag mtd: spi-nor: use BIT() for flash_info flags mtd: spi-nor: disallow further writes to SR if WP# is low mtd: spi-nor: make lock/unlock bounds checks more obvious and robust mtd: spi-nor: silently drop lock/unlock for already locked/unlocked region mtd: spi-nor: wait for SR_WIP to clear on initial unlock mtd: nand: simplify nand_bch_init() usage mtd: mtdswap: remove useless if (!mtd->ecclayout) test mtd: create an mtd_oobavail() helper and make use of it mtd: kill the ecclayout->oobavail field mtd: nand: check status before reporting timeout mtd: bcm63xxpart: give width specifier an 'int', not 'size_t' mtd: mtdram: Add parameter for setting writebuf size mtd: nand: pxa3xx_nand: kill unused field 'drcmr_cmd' ...
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@@ -166,7 +166,6 @@ struct bbm_info {
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};
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/* OneNAND BBT interface */
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extern int onenand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
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extern int onenand_default_bbt(struct mtd_info *mtd);
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#endif /* __LINUX_MTD_BBM_H */
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@@ -44,7 +44,6 @@ struct INFTLrecord {
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unsigned int nb_blocks; /* number of physical blocks */
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unsigned int nb_boot_blocks; /* number of blocks used by the bios */
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struct erase_info instr;
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struct nand_ecclayout oobinfo;
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};
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int INFTL_mount(struct INFTLrecord *s);
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@@ -240,8 +240,11 @@ struct map_info {
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If there is no cache to care about this can be set to NULL. */
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void (*inval_cache)(struct map_info *, unsigned long, ssize_t);
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/* set_vpp() must handle being reentered -- enable, enable, disable
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must leave it enabled. */
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/* This will be called with 1 as parameter when the first map user
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* needs VPP, and called with 0 when the last user exits. The map
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* core maintains a reference counter, and assumes that VPP is a
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* global resource applying to all mapped flash chips on the system.
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*/
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void (*set_vpp)(struct map_info *, int);
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unsigned long pfow_base;
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@@ -105,7 +105,6 @@ struct mtd_oob_ops {
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struct nand_ecclayout {
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__u32 eccbytes;
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__u32 eccpos[MTD_MAX_ECCPOS_ENTRIES_LARGE];
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__u32 oobavail;
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struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES_LARGE];
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};
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@@ -265,6 +264,11 @@ static inline struct device_node *mtd_get_of_node(struct mtd_info *mtd)
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return mtd->dev.of_node;
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}
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static inline int mtd_oobavail(struct mtd_info *mtd, struct mtd_oob_ops *ops)
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{
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return ops->mode == MTD_OPS_AUTO_OOB ? mtd->oobavail : mtd->oobsize;
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}
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int mtd_erase(struct mtd_info *mtd, struct erase_info *instr);
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int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
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void **virt, resource_size_t *phys);
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@@ -168,6 +168,12 @@ typedef enum {
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/* Device supports subpage reads */
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#define NAND_SUBPAGE_READ 0x00001000
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/*
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* Some MLC NANDs need data scrambling to limit bitflips caused by repeated
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* patterns.
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*/
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#define NAND_NEED_SCRAMBLING 0x00002000
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/* Options valid for Samsung large page devices */
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#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
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@@ -666,7 +672,7 @@ struct nand_chip {
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void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
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void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
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void (*select_chip)(struct mtd_info *mtd, int chip);
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int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
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int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
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int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
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void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
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int (*dev_ready)(struct mtd_info *mtd);
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@@ -896,7 +902,6 @@ extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
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* @chip_delay: R/B delay value in us
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* @options: Option flags, e.g. 16bit buswidth
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* @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
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* @ecclayout: ECC layout info structure
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* @part_probe_types: NULL-terminated array of probe types
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*/
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struct platform_nand_chip {
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@@ -904,7 +909,6 @@ struct platform_nand_chip {
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int chip_offset;
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int nr_partitions;
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struct mtd_partition *partitions;
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struct nand_ecclayout *ecclayout;
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int chip_delay;
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unsigned int options;
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unsigned int bbt_options;
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@@ -32,9 +32,7 @@ int nand_bch_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc,
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/*
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* Initialize BCH encoder/decoder
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*/
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struct nand_bch_control *
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nand_bch_init(struct mtd_info *mtd, unsigned int eccsize,
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unsigned int eccbytes, struct nand_ecclayout **ecclayout);
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struct nand_bch_control *nand_bch_init(struct mtd_info *mtd);
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/*
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* Release BCH encoder/decoder resources
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*/
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@@ -58,9 +56,7 @@ nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf,
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return -ENOTSUPP;
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}
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static inline struct nand_bch_control *
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nand_bch_init(struct mtd_info *mtd, unsigned int eccsize,
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unsigned int eccbytes, struct nand_ecclayout **ecclayout)
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static inline struct nand_bch_control *nand_bch_init(struct mtd_info *mtd)
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{
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return NULL;
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}
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@@ -50,7 +50,6 @@ struct NFTLrecord {
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unsigned int nb_blocks; /* number of physical blocks */
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unsigned int nb_boot_blocks; /* number of blocks used by the bios */
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struct erase_info instr;
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struct nand_ecclayout oobinfo;
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};
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int NFTL_mount(struct NFTLrecord *s);
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@@ -85,6 +85,7 @@
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#define SR_BP0 BIT(2) /* Block protect 0 */
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#define SR_BP1 BIT(3) /* Block protect 1 */
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#define SR_BP2 BIT(4) /* Block protect 2 */
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#define SR_TB BIT(5) /* Top/Bottom protect */
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#define SR_SRWD BIT(7) /* SR write protect */
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#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
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@@ -116,6 +117,7 @@ enum spi_nor_ops {
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enum spi_nor_option_flags {
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SNOR_F_USE_FSR = BIT(0),
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SNOR_F_HAS_SR_TB = BIT(1),
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};
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/**
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@@ -40,7 +40,6 @@ struct s3c2410_nand_set {
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char *name;
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int *nr_map;
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struct mtd_partition *partitions;
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struct nand_ecclayout *ecc_layout;
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};
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struct s3c2410_platform_nand {
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