Merge tag 'drm-intel-next-2018-04-13' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
First drm/i915 feature batch heading for v4.18: - drm-next backmerge to fix build (Rodrigo) - GPU documentation improvements (Kevin) - GuC and HuC refactoring, host/GuC communication, logging, fixes, and more (mostly Michal and Michał, also Jackie, Michel and Piotr) - PSR and PSR2 enabling and fixes (DK, José, Rodrigo and Chris) - Selftest updates (Chris, Daniele) - DPLL management refactoring (Lucas) - DP MST fixes (Lyude and DK) - Watermark refactoring and changes to support NV12 (Mahesh) - NV12 prep work (Chandra) - Icelake Combo PHY enablers (Manasi) - Perf OA refactoring and ICL enabling (Lionel) - ICL enabling (Oscar, Paulo, Nabendu, Mika, Kelvin, Michel) - Workarounds refactoring (Oscar) - HDCP fixes and improvements (Ramalingam, Radhakrishna) - Power management fixes (Imre) - Various display fixes (Maarten, Ville, Vidya, Jani, Gaurav) - debugfs for FIFO underrun clearing (Maarten) - Execlist improvements (Chris) - Reset improvements (Chris) - Plenty of things here and there I overlooked and/or didn't understand... (Everyone) Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/87lgd2cze8.fsf@intel.com
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Dave Airlie
@@ -58,6 +58,12 @@ Intel GVT-g Host Support(vGPU device model)
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.. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
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:internal:
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Workarounds
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-----------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_workarounds.c
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:doc: Hardware workarounds
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Display Hardware Handling
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=========================
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@@ -249,6 +255,103 @@ Memory Management and Command Submission
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This sections covers all things related to the GEM implementation in the
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i915 driver.
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Intel GPU Basics
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----------------
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An Intel GPU has multiple engines. There are several engine types.
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- RCS engine is for rendering 3D and performing compute, this is named
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`I915_EXEC_RENDER` in user space.
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- BCS is a blitting (copy) engine, this is named `I915_EXEC_BLT` in user
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space.
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- VCS is a video encode and decode engine, this is named `I915_EXEC_BSD`
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in user space
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- VECS is video enhancement engine, this is named `I915_EXEC_VEBOX` in user
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space.
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- The enumeration `I915_EXEC_DEFAULT` does not refer to specific engine;
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instead it is to be used by user space to specify a default rendering
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engine (for 3D) that may or may not be the same as RCS.
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The Intel GPU family is a family of integrated GPU's using Unified
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Memory Access. For having the GPU "do work", user space will feed the
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GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2`
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or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will
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instruct the GPU to perform work (for example rendering) and that work
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needs memory from which to read and memory to which to write. All memory
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is encapsulated within GEM buffer objects (usually created with the ioctl
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`DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU
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to create will also list all GEM buffer objects that the batchbuffer reads
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and/or writes. For implementation details of memory management see
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`GEM BO Management Implementation Details`_.
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The i915 driver allows user space to create a context via the ioctl
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`DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit
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integer. Such a context should be viewed by user-space as -loosely-
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analogous to the idea of a CPU process of an operating system. The i915
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driver guarantees that commands issued to a fixed context are to be
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executed so that writes of a previously issued command are seen by
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reads of following commands. Actions issued between different contexts
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(even if from the same file descriptor) are NOT given that guarantee
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and the only way to synchronize across contexts (even from the same
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file descriptor) is through the use of fences. At least as far back as
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Gen4, also have that a context carries with it a GPU HW context;
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the HW context is essentially (most of atleast) the state of a GPU.
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In addition to the ordering guarantees, the kernel will restore GPU
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state via HW context when commands are issued to a context, this saves
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user space the need to restore (most of atleast) the GPU state at the
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start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer
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work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1)
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to identify what context to use with the command.
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The GPU has its own memory management and address space. The kernel
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driver maintains the memory translation table for the GPU. For older
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GPUs (i.e. those before Gen8), there is a single global such translation
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table, a global Graphics Translation Table (GTT). For newer generation
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GPUs each context has its own translation table, called Per-Process
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Graphics Translation Table (PPGTT). Of important note, is that although
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PPGTT is named per-process it is actually per context. When user space
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submits a batchbuffer, the kernel walks the list of GEM buffer objects
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used by the batchbuffer and guarantees that not only is the memory of
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each such GEM buffer object resident but it is also present in the
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(PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT,
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then it is given an address. Two consequences of this are: the kernel
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needs to edit the batchbuffer submitted to write the correct value of
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the GPU address when a GEM BO is assigned a GPU address and the kernel
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might evict a different GEM BO from the (PP)GTT to make address room
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for another GEM BO. Consequently, the ioctls submitting a batchbuffer
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for execution also include a list of all locations within buffers that
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refer to GPU-addresses so that the kernel can edit the buffer correctly.
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This process is dubbed relocation.
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GEM BO Management Implementation Details
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----------------------------------------
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.. kernel-doc:: drivers/gpu/drm/i915/i915_vma.h
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:doc: Virtual Memory Address
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Buffer Object Eviction
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----------------------
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This section documents the interface functions for evicting buffer
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objects to make space available in the virtual gpu address spaces. Note
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that this is mostly orthogonal to shrinking buffer objects caches, which
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has the goal to make main memory (shared with the gpu through the
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unified memory architecture) available.
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.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_evict.c
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:internal:
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Buffer Object Memory Shrinking
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------------------------------
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This section documents the interface function for shrinking memory usage
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of buffer object caches. Shrinking is used to make main memory
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available. Note that this is mostly orthogonal to evicting buffer
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objects, which has the goal to make space in gpu virtual address spaces.
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.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_shrinker.c
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:internal:
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Batchbuffer Parsing
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-------------------
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@@ -267,6 +370,12 @@ Batchbuffer Pools
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.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_batch_pool.c
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:internal:
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User Batchbuffer Execution
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--------------------------
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.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_execbuffer.c
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:doc: User command execution
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Logical Rings, Logical Ring Contexts and Execlists
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--------------------------------------------------
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@@ -312,28 +421,14 @@ Object Tiling IOCTLs
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.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_tiling.c
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:doc: buffer object tiling
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Buffer Object Eviction
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----------------------
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WOPCM
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=====
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This section documents the interface functions for evicting buffer
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objects to make space available in the virtual gpu address spaces. Note
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that this is mostly orthogonal to shrinking buffer objects caches, which
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has the goal to make main memory (shared with the gpu through the
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unified memory architecture) available.
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WOPCM Layout
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------------
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.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_evict.c
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:internal:
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Buffer Object Memory Shrinking
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------------------------------
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This section documents the interface function for shrinking memory usage
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of buffer object caches. Shrinking is used to make main memory
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available. Note that this is mostly orthogonal to evicting buffer
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objects, which has the goal to make space in gpu virtual address spaces.
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.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_shrinker.c
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:internal:
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.. kernel-doc:: drivers/gpu/drm/i915/intel_wopcm.c
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:doc: WOPCM Layout
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GuC
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===
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@@ -359,6 +454,12 @@ GuC Firmware Layout
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.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fwif.h
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:doc: GuC Firmware Layout
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GuC Address Space
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-----------------
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.. kernel-doc:: drivers/gpu/drm/i915/intel_guc.c
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:doc: GuC Address Space
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Tracing
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=======
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新增問題並參考
封鎖使用者