ARM: EXYNOS: Add usb otg phy control for EXYNOS4210
This patch supports to control usb otg phy of EXYNOS4210. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> [Rebased on the newest git/kgene/linux-samsung #for-next] Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> [kgene.kim@samsung.com: squashed 2 patches together] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Šī revīzija ir iekļauta:

revīziju iesūtīja
Kukjin Kim

vecāks
36be50515f
revīzija
8ea2d9e7de
@@ -26,11 +26,71 @@ static int exynos4_usb_host_phy_is_on(void)
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return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1;
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}
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static int exynos4_usb_phy1_init(struct platform_device *pdev)
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static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
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{
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struct clk *otg_clk;
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struct clk *xusbxti_clk;
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u32 phyclk;
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/* set clock frequency for PLL */
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phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK;
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xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
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if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
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switch (clk_get_rate(xusbxti_clk)) {
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case 12 * MHZ:
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phyclk |= CLKSEL_12M;
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break;
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case 24 * MHZ:
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phyclk |= CLKSEL_24M;
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break;
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default:
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case 48 * MHZ:
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/* default reference clock */
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break;
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}
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clk_put(xusbxti_clk);
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}
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writel(phyclk, EXYNOS4_PHYCLK);
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}
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static int exynos4210_usb_phy0_init(struct platform_device *pdev)
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{
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u32 rstcon;
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writel(readl(S5P_USBDEVICE_PHY_CONTROL) | S5P_USBDEVICE_PHY_ENABLE,
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S5P_USBDEVICE_PHY_CONTROL);
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exynos4210_usb_phy_clkset(pdev);
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/* set to normal PHY0 */
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writel((readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK), EXYNOS4_PHYPWR);
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/* reset PHY0 and Link */
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rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
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writel(rstcon, EXYNOS4_RSTCON);
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udelay(10);
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rstcon &= ~PHY0_SWRST_MASK;
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writel(rstcon, EXYNOS4_RSTCON);
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return 0;
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}
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static int exynos4210_usb_phy0_exit(struct platform_device *pdev)
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{
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writel((readl(EXYNOS4_PHYPWR) | PHY0_ANALOG_POWERDOWN |
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PHY0_OTG_DISABLE), EXYNOS4_PHYPWR);
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writel(readl(S5P_USBDEVICE_PHY_CONTROL) & ~S5P_USBDEVICE_PHY_ENABLE,
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S5P_USBDEVICE_PHY_CONTROL);
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return 0;
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}
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static int exynos4210_usb_phy1_init(struct platform_device *pdev)
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{
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struct clk *otg_clk;
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u32 rstcon;
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int err;
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@@ -54,27 +114,7 @@ static int exynos4_usb_phy1_init(struct platform_device *pdev)
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writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE,
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S5P_USBHOST_PHY_CONTROL);
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/* set clock frequency for PLL */
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phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK;
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xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
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if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
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switch (clk_get_rate(xusbxti_clk)) {
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case 12 * MHZ:
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phyclk |= CLKSEL_12M;
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break;
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case 24 * MHZ:
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phyclk |= CLKSEL_24M;
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break;
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default:
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case 48 * MHZ:
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/* default reference clock */
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break;
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}
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clk_put(xusbxti_clk);
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}
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writel(phyclk, EXYNOS4_PHYCLK);
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exynos4210_usb_phy_clkset(pdev);
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/* floating prevention logic: disable */
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writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
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@@ -102,7 +142,7 @@ static int exynos4_usb_phy1_init(struct platform_device *pdev)
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return 0;
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}
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static int exynos4_usb_phy1_exit(struct platform_device *pdev)
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static int exynos4210_usb_phy1_exit(struct platform_device *pdev)
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{
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struct clk *otg_clk;
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int err;
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@@ -136,16 +176,20 @@ static int exynos4_usb_phy1_exit(struct platform_device *pdev)
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int s5p_usb_phy_init(struct platform_device *pdev, int type)
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{
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if (type == S5P_USB_PHY_HOST)
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return exynos4_usb_phy1_init(pdev);
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if (type == S5P_USB_PHY_DEVICE)
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return exynos4210_usb_phy0_init(pdev);
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else if (type == S5P_USB_PHY_HOST)
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return exynos4210_usb_phy1_init(pdev);
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return -EINVAL;
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}
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int s5p_usb_phy_exit(struct platform_device *pdev, int type)
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{
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if (type == S5P_USB_PHY_HOST)
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return exynos4_usb_phy1_exit(pdev);
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if (type == S5P_USB_PHY_DEVICE)
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return exynos4210_usb_phy0_exit(pdev);
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else if (type == S5P_USB_PHY_HOST)
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return exynos4210_usb_phy1_exit(pdev);
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return -EINVAL;
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}
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