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arm64: flush: use local TLB and I-cache invalidation

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There are a number of places where a single CPU is running with a
private page-table and we need to perform maintenance on the TLB and
I-cache in order to ensure correctness, but do not require the operation
to be broadcast to other CPUs.

This patch adds local variants of tlb_flush_all and __flush_icache_all
to support these use-cases and updates the callers respectively.
__local_flush_icache_all also implies an isb, since it is intended to be
used synchronously.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: David Daney <david.daney@cavium.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Will Deacon
2015-10-06 18:46:23 +01:00
committed by Catalin Marinas
parent fa7aae8a42
commit 8e63d38876
7 changed files with 22 additions and 7 deletions
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4
arch/arm64/kernel/efi.c
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@@ -344,9 +344,9 @@ static void efi_set_pgd(struct mm_struct *mm)
else
cpu_switch_mm(mm->pgd, mm);
flush_tlb_all();
local_flush_tlb_all();
if (icache_is_aivivt())
__flush_icache_all();
__local_flush_icache_all();
}
void efi_virtmap_load(void)