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powerpc/mm/book3s64: Fix possible build error

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[ Upstream commit 07d8ad6fd8a3d47f50595ca4826f41dbf4f3a0c6 ]

Update _tlbiel_pid() such that we can avoid build errors like below when
using this function in other places.

arch/powerpc/mm/book3s64/radix_tlb.c: In function ‘__radix__flush_tlb_range_psize’:
arch/powerpc/mm/book3s64/radix_tlb.c:114:2: warning: ‘asm’ operand 3 probably does not match constraints
  114 |  asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
      |  ^~~
arch/powerpc/mm/book3s64/radix_tlb.c:114:2: error: impossible constraint in ‘asm’
make[4]: *** [scripts/Makefile.build:271: arch/powerpc/mm/book3s64/radix_tlb.o] Error 1
m

With this fix, we can also drop the __always_inline in __radix_flush_tlb_range_psize
which was added by commit e12d6d7d46 ("powerpc/mm/radix: mark __radix__flush_tlb_range_psize() as __always_inline")

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Acked-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210610083639.387365-1-aneesh.kumar@linux.ibm.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Aneesh Kumar K.V
2021-06-10 14:06:39 +05:30
committed by Greg Kroah-Hartman
parent ed0b4b56a9
commit 8e18158ea7
1 changed files with 17 additions and 9 deletions
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26
arch/powerpc/mm/book3s64/radix_tlb.c
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@@ -282,22 +282,30 @@ static inline void fixup_tlbie_lpid(unsigned long lpid)
/* /*
* We use 128 set in radix mode and 256 set in hpt mode. * We use 128 set in radix mode and 256 set in hpt mode.
*/ */
static __always_inline void _tlbiel_pid(unsigned long pid, unsigned long ric) static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
{ {
int set; int set;
asm volatile("ptesync": : :"memory"); asm volatile("ptesync": : :"memory");
/* switch (ric) {
* Flush the first set of the TLB, and if we're doing a RIC_FLUSH_ALL, case RIC_FLUSH_PWC:
* also flush the entire Page Walk Cache.
*/
__tlbiel_pid(pid, 0, ric);
/* For PWC, only one flush is needed */ /* For PWC, only one flush is needed */
if (ric == RIC_FLUSH_PWC) { __tlbiel_pid(pid, 0, RIC_FLUSH_PWC);
ppc_after_tlbiel_barrier(); ppc_after_tlbiel_barrier();
return; return;
case RIC_FLUSH_TLB:
__tlbiel_pid(pid, 0, RIC_FLUSH_TLB);
break;
case RIC_FLUSH_ALL:
default:
/*
* Flush the first set of the TLB, and if
* we're doing a RIC_FLUSH_ALL, also flush
* the entire Page Walk Cache.
*/
__tlbiel_pid(pid, 0, RIC_FLUSH_ALL);
} }
/* For the remaining sets, just flush the TLB */ /* For the remaining sets, just flush the TLB */
@@ -1068,7 +1076,7 @@ void radix__tlb_flush(struct mmu_gather *tlb)
} }
} }
static __always_inline void __radix__flush_tlb_range_psize(struct mm_struct *mm, static void __radix__flush_tlb_range_psize(struct mm_struct *mm,
unsigned long start, unsigned long end, unsigned long start, unsigned long end,
int psize, bool also_pwc) int psize, bool also_pwc)
{ {