Merge tag 'mfd-next-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD updates from Lee Jones: "Core Frameworks: - Set 'struct device' fwnode when registering a new device New Drivers: - Add support for ROHM BD70528 PMIC New Device Support: - Add support for LP87561 4-Phase Regulator to TI LP87565 PMIC - Add support for RK809 and RK817 to Rockchip RK808 - Add support for Lid Angle to ChromeOS core - Add support for CS47L15 CODEC to Madera core - Add support for CS47L92 CODEC to Madera core - Add support for ChromeOS (legacy) Accelerometers in ChromeOS core - Add support for Add Intel Elkhart Lake PCH to Intel LPSS New Functionality: - Provide regulator supply information when registering; madera-core - Additional Device Tree support; lp87565, madera, cros-ec, rohm,bd71837-pmic - Allow over-riding power button press via Device Tree; rohm-bd718x7 - Differentiate between running processors; cros_ec_dev Fix-ups: - Big header file update; cros_ec_commands.h - Split header per-subsystem; rohm-bd718x7 - Remove superfluous code; menelaus, cs5535-mfd, cs47lXX-tables - Trivial; sorting, coding style; intel-lpss-pci - Only remove Power Off functionality if set locally; rk808 - Make use for Power Off Prepare(); rk808 - Fix spelling mistake in header guards; stmfx - Properly free IDA resources - SPDX fixups; cs47lXX-tables, madera - Error path fixups; hi655x-pmic Bug Fixes: - Add missing break in case() statement - Repair undefined behaviour when not initialising variables; arizona-core, madera-core - Fix reference to Device Tree documentation; madera" * tag 'mfd-next-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (45 commits) mfd: hi655x-pmic: Fix missing return value check for devm_regmap_init_mmio_clk mfd: madera: Fixup SPDX headers mfd: madera: Remove some unused registers and fix some defaults mfd: intel-lpss: Release IDA resources mfd: intel-lpss: Add Intel Elkhart Lake PCH PCI IDs mfd: cs5535-mfd: Remove ifdef OLPC noise mfd: stmfx: Fix macro definition spelling dt-bindings: mfd: Add link to ROHM BD71847 Datasheet MAINAINERS: Swap words in INTEL PMIC MULTIFUNCTION DEVICE DRIVERS mfd: cros_ec_dev: Register cros_ec_accel_legacy driver as a subdevice mfd: rk808: Prepare rk805 for poweroff mfd: rk808: Check pm_power_off pointer mfd: cros_ec: differentiate SCP from EC by feature bit dt-bindings: Add binding for cros-ec-rpmsg mfd: madera: Add Madera core support for CS47L92 mfd: madera: Add Madera core support for CS47L15 mfd: madera: Update DT bindings to add additional CODECs mfd: madera: Add supply mapping for MICVDD mfd: madera: Fix potential uninitialised use of variable mfd: madera: Fix bad reference to pinctrl.txt file ...
This commit is contained in:
Linus Torvalds
@@ -19,6 +19,7 @@
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#define CROS_EC_DEV_PD_NAME "cros_pd"
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#define CROS_EC_DEV_TP_NAME "cros_tp"
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#define CROS_EC_DEV_ISH_NAME "cros_ish"
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#define CROS_EC_DEV_SCP_NAME "cros_scp"
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/*
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* The EC is unresponsive for a time after a reboot command. Add a
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@@ -14,6 +14,7 @@
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enum lp87565_device_type {
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LP87565_DEVICE_TYPE_UNKNOWN = 0,
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LP87565_DEVICE_TYPE_LP87561_Q1,
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LP87565_DEVICE_TYPE_LP87565_Q1,
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};
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@@ -246,6 +247,7 @@ enum LP87565_regulator_id {
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LP87565_BUCK_3,
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LP87565_BUCK_10,
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LP87565_BUCK_23,
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LP87565_BUCK_3210,
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};
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/**
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@@ -1,12 +1,8 @@
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// SPDX-License-Identifier: GPL-2.0
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* MFD internals for Cirrus Logic Madera codecs
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*
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* Copyright (C) 2015-2018 Cirrus Logic
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by the
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* Free Software Foundation; version 2.
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*/
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#ifndef MADERA_CORE_H
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@@ -26,15 +22,21 @@ enum madera_type {
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CS47L85 = 2,
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CS47L90 = 3,
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CS47L91 = 4,
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CS47L92 = 5,
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CS47L93 = 6,
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WM1840 = 7,
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CS47L15 = 8,
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CS42L92 = 9,
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};
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#define MADERA_MAX_CORE_SUPPLIES 2
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#define MADERA_MAX_GPIOS 40
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#define CS47L15_NUM_GPIOS 15
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#define CS47L35_NUM_GPIOS 16
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#define CS47L85_NUM_GPIOS 40
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#define CS47L90_NUM_GPIOS 38
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#define CS47L92_NUM_GPIOS 16
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#define MADERA_MAX_MICBIAS 4
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@@ -1,12 +1,8 @@
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// SPDX-License-Identifier: GPL-2.0
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Platform data for Cirrus Logic Madera codecs
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*
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* Copyright (C) 2015-2018 Cirrus Logic
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by the
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* Free Software Foundation; version 2.
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*/
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#ifndef MADERA_PDATA_H
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@@ -35,7 +31,8 @@ struct madera_codec_pdata;
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* @micvdd: Substruct of pdata for the MICVDD regulator
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* @irq_flags: Mode for primary IRQ (defaults to active low)
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* @gpio_base: Base GPIO number
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* @gpio_configs: Array of GPIO configurations (See Documentation/pinctrl.txt)
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* @gpio_configs: Array of GPIO configurations (See
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* Documentation/driver-api/pinctl.rst)
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* @n_gpio_configs: Number of entries in gpio_configs
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* @gpsw: General purpose switch mode setting. Depends on the external
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* hardware connected to the switch. (See the SW1_MODE field
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@@ -1,12 +1,8 @@
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// SPDX-License-Identifier: GPL-2.0
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Madera register definitions
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*
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* Copyright (C) 2015-2018 Cirrus Logic
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by the
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* Free Software Foundation; version 2.
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*/
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#ifndef MADERA_REGISTERS_H
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@@ -76,10 +72,14 @@
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#define MADERA_FLL1_CONTROL_4 0x174
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#define MADERA_FLL1_CONTROL_5 0x175
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#define MADERA_FLL1_CONTROL_6 0x176
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#define MADERA_FLL1_LOOP_FILTER_TEST_1 0x177
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#define MADERA_FLL1_NCO_TEST_0 0x178
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#define CS47L92_FLL1_CONTROL_7 0x177
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#define CS47L92_FLL1_CONTROL_8 0x178
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#define MADERA_FLL1_CONTROL_7 0x179
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#define CS47L92_FLL1_CONTROL_9 0x179
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#define MADERA_FLL1_EFS_2 0x17A
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#define CS47L92_FLL1_CONTROL_10 0x17A
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#define MADERA_FLL1_CONTROL_11 0x17B
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#define MADERA_FLL1_DIGITAL_TEST_1 0x17D
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#define CS47L35_FLL1_SYNCHRONISER_1 0x17F
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#define CS47L35_FLL1_SYNCHRONISER_2 0x180
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#define CS47L35_FLL1_SYNCHRONISER_3 0x181
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@@ -98,16 +98,21 @@
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#define MADERA_FLL1_SYNCHRONISER_7 0x187
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#define MADERA_FLL1_SPREAD_SPECTRUM 0x189
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#define MADERA_FLL1_GPIO_CLOCK 0x18A
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#define CS47L92_FLL1_GPIO_CLOCK 0x18E
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#define MADERA_FLL2_CONTROL_1 0x191
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#define MADERA_FLL2_CONTROL_2 0x192
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#define MADERA_FLL2_CONTROL_3 0x193
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#define MADERA_FLL2_CONTROL_4 0x194
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#define MADERA_FLL2_CONTROL_5 0x195
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#define MADERA_FLL2_CONTROL_6 0x196
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#define MADERA_FLL2_LOOP_FILTER_TEST_1 0x197
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#define MADERA_FLL2_NCO_TEST_0 0x198
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#define CS47L92_FLL2_CONTROL_7 0x197
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#define CS47L92_FLL2_CONTROL_8 0x198
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#define MADERA_FLL2_CONTROL_7 0x199
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#define CS47L92_FLL2_CONTROL_9 0x199
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#define MADERA_FLL2_EFS_2 0x19A
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#define CS47L92_FLL2_CONTROL_10 0x19A
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#define MADERA_FLL2_CONTROL_11 0x19B
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#define MADERA_FLL2_DIGITAL_TEST_1 0x19D
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#define MADERA_FLL2_SYNCHRONISER_1 0x1A1
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#define MADERA_FLL2_SYNCHRONISER_2 0x1A2
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#define MADERA_FLL2_SYNCHRONISER_3 0x1A3
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@@ -117,14 +122,13 @@
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#define MADERA_FLL2_SYNCHRONISER_7 0x1A7
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#define MADERA_FLL2_SPREAD_SPECTRUM 0x1A9
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#define MADERA_FLL2_GPIO_CLOCK 0x1AA
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#define CS47L92_FLL2_GPIO_CLOCK 0x1AE
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#define MADERA_FLL3_CONTROL_1 0x1B1
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#define MADERA_FLL3_CONTROL_2 0x1B2
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#define MADERA_FLL3_CONTROL_3 0x1B3
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#define MADERA_FLL3_CONTROL_4 0x1B4
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#define MADERA_FLL3_CONTROL_5 0x1B5
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#define MADERA_FLL3_CONTROL_6 0x1B6
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#define MADERA_FLL3_LOOP_FILTER_TEST_1 0x1B7
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#define MADERA_FLL3_NCO_TEST_0 0x1B8
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#define MADERA_FLL3_CONTROL_7 0x1B9
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#define MADERA_FLL3_SYNCHRONISER_1 0x1C1
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#define MADERA_FLL3_SYNCHRONISER_2 0x1C2
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@@ -244,6 +248,8 @@
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#define MADERA_IN6R_CONTROL 0x33C
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#define MADERA_ADC_DIGITAL_VOLUME_6R 0x33D
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#define MADERA_DMIC6R_CONTROL 0x33E
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#define CS47L15_ADC_INT_BIAS 0x3A8
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#define CS47L15_PGA_BIAS_SEL 0x3C4
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#define MADERA_OUTPUT_ENABLES_1 0x400
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#define MADERA_OUTPUT_STATUS_1 0x401
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#define MADERA_RAW_OUTPUT_STATUS_1 0x406
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@@ -265,6 +271,7 @@
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#define MADERA_NOISE_GATE_SELECT_2R 0x41F
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#define MADERA_OUTPUT_PATH_CONFIG_3L 0x420
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#define MADERA_DAC_DIGITAL_VOLUME_3L 0x421
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#define MADERA_OUTPUT_PATH_CONFIG_3 0x422
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#define MADERA_NOISE_GATE_SELECT_3L 0x423
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#define MADERA_OUTPUT_PATH_CONFIG_3R 0x424
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#define MADERA_DAC_DIGITAL_VOLUME_3R 0x425
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@@ -287,9 +294,6 @@
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#define MADERA_OUTPUT_PATH_CONFIG_6R 0x43C
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#define MADERA_DAC_DIGITAL_VOLUME_6R 0x43D
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#define MADERA_NOISE_GATE_SELECT_6R 0x43F
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#define MADERA_DRE_ENABLE 0x440
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#define MADERA_EDRE_ENABLE 0x448
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#define MADERA_EDRE_MANUAL 0x44A
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#define MADERA_DAC_AEC_CONTROL_1 0x450
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#define MADERA_DAC_AEC_CONTROL_2 0x451
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#define MADERA_NOISE_GATE_CONTROL 0x458
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@@ -367,8 +371,20 @@
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#define MADERA_AIF3_FRAME_CTRL_2 0x588
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#define MADERA_AIF3_FRAME_CTRL_3 0x589
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#define MADERA_AIF3_FRAME_CTRL_4 0x58A
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#define MADERA_AIF3_FRAME_CTRL_5 0x58B
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#define MADERA_AIF3_FRAME_CTRL_6 0x58C
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#define MADERA_AIF3_FRAME_CTRL_7 0x58D
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#define MADERA_AIF3_FRAME_CTRL_8 0x58E
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#define MADERA_AIF3_FRAME_CTRL_9 0x58F
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#define MADERA_AIF3_FRAME_CTRL_10 0x590
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#define MADERA_AIF3_FRAME_CTRL_11 0x591
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#define MADERA_AIF3_FRAME_CTRL_12 0x592
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#define MADERA_AIF3_FRAME_CTRL_13 0x593
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#define MADERA_AIF3_FRAME_CTRL_14 0x594
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#define MADERA_AIF3_FRAME_CTRL_15 0x595
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#define MADERA_AIF3_FRAME_CTRL_16 0x596
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#define MADERA_AIF3_FRAME_CTRL_17 0x597
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#define MADERA_AIF3_FRAME_CTRL_18 0x598
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#define MADERA_AIF3_TX_ENABLES 0x599
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#define MADERA_AIF3_RX_ENABLES 0x59A
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#define MADERA_AIF3_FORCE_WRITE 0x59B
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@@ -660,6 +676,54 @@
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#define MADERA_AIF3TX2MIX_INPUT_3_VOLUME 0x78D
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#define MADERA_AIF3TX2MIX_INPUT_4_SOURCE 0x78E
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#define MADERA_AIF3TX2MIX_INPUT_4_VOLUME 0x78F
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#define MADERA_AIF3TX3MIX_INPUT_1_SOURCE 0x790
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#define MADERA_AIF3TX3MIX_INPUT_1_VOLUME 0x791
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#define MADERA_AIF3TX3MIX_INPUT_2_SOURCE 0x792
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#define MADERA_AIF3TX3MIX_INPUT_2_VOLUME 0x793
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#define MADERA_AIF3TX3MIX_INPUT_3_SOURCE 0x794
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#define MADERA_AIF3TX3MIX_INPUT_3_VOLUME 0x795
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#define MADERA_AIF3TX3MIX_INPUT_4_SOURCE 0x796
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#define MADERA_AIF3TX3MIX_INPUT_4_VOLUME 0x797
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#define MADERA_AIF3TX4MIX_INPUT_1_SOURCE 0x798
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#define MADERA_AIF3TX4MIX_INPUT_1_VOLUME 0x799
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#define MADERA_AIF3TX4MIX_INPUT_2_SOURCE 0x79A
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#define MADERA_AIF3TX4MIX_INPUT_2_VOLUME 0x79B
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#define MADERA_AIF3TX4MIX_INPUT_3_SOURCE 0x79C
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#define MADERA_AIF3TX4MIX_INPUT_3_VOLUME 0x79D
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#define MADERA_AIF3TX4MIX_INPUT_4_SOURCE 0x79E
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#define MADERA_AIF3TX4MIX_INPUT_4_VOLUME 0x79F
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#define CS47L92_AIF3TX5MIX_INPUT_1_SOURCE 0x7A0
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#define CS47L92_AIF3TX5MIX_INPUT_1_VOLUME 0x7A1
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#define CS47L92_AIF3TX5MIX_INPUT_2_SOURCE 0x7A2
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#define CS47L92_AIF3TX5MIX_INPUT_2_VOLUME 0x7A3
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#define CS47L92_AIF3TX5MIX_INPUT_3_SOURCE 0x7A4
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#define CS47L92_AIF3TX5MIX_INPUT_3_VOLUME 0x7A5
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#define CS47L92_AIF3TX5MIX_INPUT_4_SOURCE 0x7A6
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#define CS47L92_AIF3TX5MIX_INPUT_4_VOLUME 0x7A7
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#define CS47L92_AIF3TX6MIX_INPUT_1_SOURCE 0x7A8
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#define CS47L92_AIF3TX6MIX_INPUT_1_VOLUME 0x7A9
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#define CS47L92_AIF3TX6MIX_INPUT_2_SOURCE 0x7AA
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#define CS47L92_AIF3TX6MIX_INPUT_2_VOLUME 0x7AB
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#define CS47L92_AIF3TX6MIX_INPUT_3_SOURCE 0x7AC
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#define CS47L92_AIF3TX6MIX_INPUT_3_VOLUME 0x7AD
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#define CS47L92_AIF3TX6MIX_INPUT_4_SOURCE 0x7AE
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#define CS47L92_AIF3TX6MIX_INPUT_4_VOLUME 0x7AF
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#define CS47L92_AIF3TX7MIX_INPUT_1_SOURCE 0x7B0
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#define CS47L92_AIF3TX7MIX_INPUT_1_VOLUME 0x7B1
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#define CS47L92_AIF3TX7MIX_INPUT_2_SOURCE 0x7B2
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#define CS47L92_AIF3TX7MIX_INPUT_2_VOLUME 0x7B3
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#define CS47L92_AIF3TX7MIX_INPUT_3_SOURCE 0x7B4
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#define CS47L92_AIF3TX7MIX_INPUT_3_VOLUME 0x7B5
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#define CS47L92_AIF3TX7MIX_INPUT_4_SOURCE 0x7B6
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#define CS47L92_AIF3TX7MIX_INPUT_4_VOLUME 0x7B7
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#define CS47L92_AIF3TX8MIX_INPUT_1_SOURCE 0x7B8
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#define CS47L92_AIF3TX8MIX_INPUT_1_VOLUME 0x7B9
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#define CS47L92_AIF3TX8MIX_INPUT_2_SOURCE 0x7BA
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#define CS47L92_AIF3TX8MIX_INPUT_2_VOLUME 0x7BB
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#define CS47L92_AIF3TX8MIX_INPUT_3_SOURCE 0x7BC
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#define CS47L92_AIF3TX8MIX_INPUT_3_VOLUME 0x7BD
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#define CS47L92_AIF3TX8MIX_INPUT_4_SOURCE 0x7BE
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#define CS47L92_AIF3TX8MIX_INPUT_4_VOLUME 0x7BF
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#define MADERA_AIF4TX1MIX_INPUT_1_SOURCE 0x7A0
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#define MADERA_AIF4TX1MIX_INPUT_1_VOLUME 0x7A1
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#define MADERA_AIF4TX1MIX_INPUT_2_SOURCE 0x7A2
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@@ -1103,68 +1167,8 @@
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#define MADERA_FCR_ADC_REFORMATTER_CONTROL 0xF73
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#define MADERA_FCR_COEFF_START 0xF74
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#define MADERA_FCR_COEFF_END 0xFC5
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#define MADERA_DAC_COMP_1 0x1300
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#define MADERA_DAC_COMP_2 0x1302
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#define MADERA_FRF_COEFFICIENT_1L_1 0x1380
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#define MADERA_FRF_COEFFICIENT_1L_2 0x1381
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#define MADERA_FRF_COEFFICIENT_1L_3 0x1382
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#define MADERA_FRF_COEFFICIENT_1L_4 0x1383
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#define MADERA_FRF_COEFFICIENT_1R_1 0x1390
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#define MADERA_FRF_COEFFICIENT_1R_2 0x1391
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#define MADERA_FRF_COEFFICIENT_1R_3 0x1392
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||||
#define MADERA_FRF_COEFFICIENT_1R_4 0x1393
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||||
#define MADERA_FRF_COEFFICIENT_2L_1 0x13A0
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||||
#define MADERA_FRF_COEFFICIENT_2L_2 0x13A1
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#define MADERA_FRF_COEFFICIENT_2L_3 0x13A2
|
||||
#define MADERA_FRF_COEFFICIENT_2L_4 0x13A3
|
||||
#define MADERA_FRF_COEFFICIENT_2R_1 0x13B0
|
||||
#define MADERA_FRF_COEFFICIENT_2R_2 0x13B1
|
||||
#define MADERA_FRF_COEFFICIENT_2R_3 0x13B2
|
||||
#define MADERA_FRF_COEFFICIENT_2R_4 0x13B3
|
||||
#define MADERA_FRF_COEFFICIENT_3L_1 0x13C0
|
||||
#define MADERA_FRF_COEFFICIENT_3L_2 0x13C1
|
||||
#define MADERA_FRF_COEFFICIENT_3L_3 0x13C2
|
||||
#define MADERA_FRF_COEFFICIENT_3L_4 0x13C3
|
||||
#define MADERA_FRF_COEFFICIENT_3R_1 0x13D0
|
||||
#define MADERA_FRF_COEFFICIENT_3R_2 0x13D1
|
||||
#define MADERA_FRF_COEFFICIENT_3R_3 0x13D2
|
||||
#define MADERA_FRF_COEFFICIENT_3R_4 0x13D3
|
||||
#define MADERA_FRF_COEFFICIENT_4L_1 0x13E0
|
||||
#define MADERA_FRF_COEFFICIENT_4L_2 0x13E1
|
||||
#define MADERA_FRF_COEFFICIENT_4L_3 0x13E2
|
||||
#define MADERA_FRF_COEFFICIENT_4L_4 0x13E3
|
||||
#define MADERA_FRF_COEFFICIENT_4R_1 0x13F0
|
||||
#define MADERA_FRF_COEFFICIENT_4R_2 0x13F1
|
||||
#define MADERA_FRF_COEFFICIENT_4R_3 0x13F2
|
||||
#define MADERA_FRF_COEFFICIENT_4R_4 0x13F3
|
||||
#define CS47L35_FRF_COEFFICIENT_4L_1 0x13A0
|
||||
#define CS47L35_FRF_COEFFICIENT_4L_2 0x13A1
|
||||
#define CS47L35_FRF_COEFFICIENT_4L_3 0x13A2
|
||||
#define CS47L35_FRF_COEFFICIENT_4L_4 0x13A3
|
||||
#define CS47L35_FRF_COEFFICIENT_5L_1 0x13B0
|
||||
#define CS47L35_FRF_COEFFICIENT_5L_2 0x13B1
|
||||
#define CS47L35_FRF_COEFFICIENT_5L_3 0x13B2
|
||||
#define CS47L35_FRF_COEFFICIENT_5L_4 0x13B3
|
||||
#define CS47L35_FRF_COEFFICIENT_5R_1 0x13C0
|
||||
#define CS47L35_FRF_COEFFICIENT_5R_2 0x13C1
|
||||
#define CS47L35_FRF_COEFFICIENT_5R_3 0x13C2
|
||||
#define CS47L35_FRF_COEFFICIENT_5R_4 0x13C3
|
||||
#define MADERA_FRF_COEFFICIENT_5L_1 0x1400
|
||||
#define MADERA_FRF_COEFFICIENT_5L_2 0x1401
|
||||
#define MADERA_FRF_COEFFICIENT_5L_3 0x1402
|
||||
#define MADERA_FRF_COEFFICIENT_5L_4 0x1403
|
||||
#define MADERA_FRF_COEFFICIENT_5R_1 0x1410
|
||||
#define MADERA_FRF_COEFFICIENT_5R_2 0x1411
|
||||
#define MADERA_FRF_COEFFICIENT_5R_3 0x1412
|
||||
#define MADERA_FRF_COEFFICIENT_5R_4 0x1413
|
||||
#define MADERA_FRF_COEFFICIENT_6L_1 0x1420
|
||||
#define MADERA_FRF_COEFFICIENT_6L_2 0x1421
|
||||
#define MADERA_FRF_COEFFICIENT_6L_3 0x1422
|
||||
#define MADERA_FRF_COEFFICIENT_6L_4 0x1423
|
||||
#define MADERA_FRF_COEFFICIENT_6R_1 0x1430
|
||||
#define MADERA_FRF_COEFFICIENT_6R_2 0x1431
|
||||
#define MADERA_FRF_COEFFICIENT_6R_3 0x1432
|
||||
#define MADERA_FRF_COEFFICIENT_6R_4 0x1433
|
||||
#define MADERA_AUXPDM1_CTRL_0 0x10C0
|
||||
#define MADERA_AUXPDM1_CTRL_1 0x10C1
|
||||
#define MADERA_DFC1_CTRL 0x1480
|
||||
#define MADERA_DFC1_RX 0x1482
|
||||
#define MADERA_DFC1_TX 0x1484
|
||||
@@ -1202,6 +1206,8 @@
|
||||
#define MADERA_GPIO1_CTRL_2 0x1701
|
||||
#define MADERA_GPIO2_CTRL_1 0x1702
|
||||
#define MADERA_GPIO2_CTRL_2 0x1703
|
||||
#define MADERA_GPIO15_CTRL_1 0x171C
|
||||
#define MADERA_GPIO15_CTRL_2 0x171D
|
||||
#define MADERA_GPIO16_CTRL_1 0x171E
|
||||
#define MADERA_GPIO16_CTRL_2 0x171F
|
||||
#define MADERA_GPIO38_CTRL_1 0x174A
|
||||
@@ -1232,6 +1238,7 @@
|
||||
#define MADERA_IRQ2_CTRL 0x1A82
|
||||
#define MADERA_INTERRUPT_RAW_STATUS_1 0x1AA0
|
||||
#define MADERA_WSEQ_SEQUENCE_1 0x3000
|
||||
#define MADERA_WSEQ_SEQUENCE_225 0x31C0
|
||||
#define MADERA_WSEQ_SEQUENCE_252 0x31F6
|
||||
#define CS47L35_OTP_HPDET_CAL_1 0x31F8
|
||||
#define CS47L35_OTP_HPDET_CAL_2 0x31FA
|
||||
@@ -1441,6 +1448,12 @@
|
||||
#define MADERA_OPCLK_ASYNC_SEL_WIDTH 3
|
||||
|
||||
/* (0x0171) FLL1_Control_1 */
|
||||
#define CS47L92_FLL1_REFCLK_SRC_MASK 0xF000
|
||||
#define CS47L92_FLL1_REFCLK_SRC_SHIFT 12
|
||||
#define CS47L92_FLL1_REFCLK_SRC_WIDTH 4
|
||||
#define MADERA_FLL1_HOLD_MASK 0x0004
|
||||
#define MADERA_FLL1_HOLD_SHIFT 2
|
||||
#define MADERA_FLL1_HOLD_WIDTH 1
|
||||
#define MADERA_FLL1_FREERUN 0x0002
|
||||
#define MADERA_FLL1_FREERUN_MASK 0x0002
|
||||
#define MADERA_FLL1_FREERUN_SHIFT 1
|
||||
@@ -1473,6 +1486,9 @@
|
||||
#define MADERA_FLL1_FRATIO_MASK 0x0F00
|
||||
#define MADERA_FLL1_FRATIO_SHIFT 8
|
||||
#define MADERA_FLL1_FRATIO_WIDTH 4
|
||||
#define MADERA_FLL1_FB_DIV_MASK 0x03FF
|
||||
#define MADERA_FLL1_FB_DIV_SHIFT 0
|
||||
#define MADERA_FLL1_FB_DIV_WIDTH 10
|
||||
|
||||
/* (0x0176) FLL1_Control_6 */
|
||||
#define MADERA_FLL1_REFCLK_DIV_MASK 0x00C0
|
||||
@@ -1482,15 +1498,6 @@
|
||||
#define MADERA_FLL1_REFCLK_SRC_SHIFT 0
|
||||
#define MADERA_FLL1_REFCLK_SRC_WIDTH 4
|
||||
|
||||
/* (0x0177) FLL1_Loop_Filter_Test_1 */
|
||||
#define MADERA_FLL1_FRC_INTEG_UPD 0x8000
|
||||
#define MADERA_FLL1_FRC_INTEG_UPD_MASK 0x8000
|
||||
#define MADERA_FLL1_FRC_INTEG_UPD_SHIFT 15
|
||||
#define MADERA_FLL1_FRC_INTEG_UPD_WIDTH 1
|
||||
#define MADERA_FLL1_FRC_INTEG_VAL_MASK 0x0FFF
|
||||
#define MADERA_FLL1_FRC_INTEG_VAL_SHIFT 0
|
||||
#define MADERA_FLL1_FRC_INTEG_VAL_WIDTH 12
|
||||
|
||||
/* (0x0179) FLL1_Control_7 */
|
||||
#define MADERA_FLL1_GAIN_MASK 0x003c
|
||||
#define MADERA_FLL1_GAIN_SHIFT 2
|
||||
@@ -1504,6 +1511,30 @@
|
||||
#define MADERA_FLL1_PHASE_ENA_SHIFT 11
|
||||
#define MADERA_FLL1_PHASE_ENA_WIDTH 1
|
||||
|
||||
/* (0x017A) FLL1_Control_10 */
|
||||
#define MADERA_FLL1_HP_MASK 0xC000
|
||||
#define MADERA_FLL1_HP_SHIFT 14
|
||||
#define MADERA_FLL1_HP_WIDTH 2
|
||||
#define MADERA_FLL1_PHASEDET_ENA_MASK 0x1000
|
||||
#define MADERA_FLL1_PHASEDET_ENA_SHIFT 12
|
||||
#define MADERA_FLL1_PHASEDET_ENA_WIDTH 1
|
||||
|
||||
/* (0x017B) FLL1_Control_11 */
|
||||
#define MADERA_FLL1_LOCKDET_THR_MASK 0x001E
|
||||
#define MADERA_FLL1_LOCKDET_THR_SHIFT 1
|
||||
#define MADERA_FLL1_LOCKDET_THR_WIDTH 4
|
||||
#define MADERA_FLL1_LOCKDET_MASK 0x0001
|
||||
#define MADERA_FLL1_LOCKDET_SHIFT 0
|
||||
#define MADERA_FLL1_LOCKDET_WIDTH 1
|
||||
|
||||
/* (0x017D) FLL1_Digital_Test_1 */
|
||||
#define MADERA_FLL1_SYNC_EFS_ENA_MASK 0x0100
|
||||
#define MADERA_FLL1_SYNC_EFS_ENA_SHIFT 8
|
||||
#define MADERA_FLL1_SYNC_EFS_ENA_WIDTH 1
|
||||
#define MADERA_FLL1_CLK_VCO_FAST_SRC_MASK 0x0003
|
||||
#define MADERA_FLL1_CLK_VCO_FAST_SRC_SHIFT 0
|
||||
#define MADERA_FLL1_CLK_VCO_FAST_SRC_WIDTH 2
|
||||
|
||||
/* (0x0181) FLL1_Synchroniser_1 */
|
||||
#define MADERA_FLL1_SYNC_ENA 0x0001
|
||||
#define MADERA_FLL1_SYNC_ENA_MASK 0x0001
|
||||
@@ -1625,6 +1656,13 @@
|
||||
#define MADERA_LDO2_ENA_WIDTH 1
|
||||
|
||||
/* (0x0218) Mic_Bias_Ctrl_1 */
|
||||
#define MADERA_MICB1_EXT_CAP 0x8000
|
||||
#define MADERA_MICB1_EXT_CAP_MASK 0x8000
|
||||
#define MADERA_MICB1_EXT_CAP_SHIFT 15
|
||||
#define MADERA_MICB1_EXT_CAP_WIDTH 1
|
||||
#define MADERA_MICB1_LVL_MASK 0x01E0
|
||||
#define MADERA_MICB1_LVL_SHIFT 5
|
||||
#define MADERA_MICB1_LVL_WIDTH 4
|
||||
#define MADERA_MICB1_ENA 0x0001
|
||||
#define MADERA_MICB1_ENA_MASK 0x0001
|
||||
#define MADERA_MICB1_ENA_SHIFT 0
|
||||
@@ -2308,6 +2346,17 @@
|
||||
#define MADERA_OUT1R_ENA_SHIFT 0
|
||||
#define MADERA_OUT1R_ENA_WIDTH 1
|
||||
|
||||
/* (0x0408) Output_Rate_1 */
|
||||
#define MADERA_CP_DAC_MODE_MASK 0x0040
|
||||
#define MADERA_CP_DAC_MODE_SHIFT 6
|
||||
#define MADERA_CP_DAC_MODE_WIDTH 1
|
||||
#define MADERA_OUT_EXT_CLK_DIV_MASK 0x0030
|
||||
#define MADERA_OUT_EXT_CLK_DIV_SHIFT 4
|
||||
#define MADERA_OUT_EXT_CLK_DIV_WIDTH 2
|
||||
#define MADERA_OUT_CLK_SRC_MASK 0x0007
|
||||
#define MADERA_OUT_CLK_SRC_SHIFT 0
|
||||
#define MADERA_OUT_CLK_SRC_WIDTH 3
|
||||
|
||||
/* (0x0409) Output_Volume_Ramp */
|
||||
#define MADERA_OUT_VD_RAMP_MASK 0x0070
|
||||
#define MADERA_OUT_VD_RAMP_SHIFT 4
|
||||
@@ -2829,6 +2878,30 @@
|
||||
#define MADERA_AIF2RX1_ENA_WIDTH 1
|
||||
|
||||
/* (0x0599) AIF3_Tx_Enables */
|
||||
#define MADERA_AIF3TX8_ENA 0x0080
|
||||
#define MADERA_AIF3TX8_ENA_MASK 0x0080
|
||||
#define MADERA_AIF3TX8_ENA_SHIFT 7
|
||||
#define MADERA_AIF3TX8_ENA_WIDTH 1
|
||||
#define MADERA_AIF3TX7_ENA 0x0040
|
||||
#define MADERA_AIF3TX7_ENA_MASK 0x0040
|
||||
#define MADERA_AIF3TX7_ENA_SHIFT 6
|
||||
#define MADERA_AIF3TX7_ENA_WIDTH 1
|
||||
#define MADERA_AIF3TX6_ENA 0x0020
|
||||
#define MADERA_AIF3TX6_ENA_MASK 0x0020
|
||||
#define MADERA_AIF3TX6_ENA_SHIFT 5
|
||||
#define MADERA_AIF3TX6_ENA_WIDTH 1
|
||||
#define MADERA_AIF3TX5_ENA 0x0010
|
||||
#define MADERA_AIF3TX5_ENA_MASK 0x0010
|
||||
#define MADERA_AIF3TX5_ENA_SHIFT 4
|
||||
#define MADERA_AIF3TX5_ENA_WIDTH 1
|
||||
#define MADERA_AIF3TX4_ENA 0x0008
|
||||
#define MADERA_AIF3TX4_ENA_MASK 0x0008
|
||||
#define MADERA_AIF3TX4_ENA_SHIFT 3
|
||||
#define MADERA_AIF3TX4_ENA_WIDTH 1
|
||||
#define MADERA_AIF3TX3_ENA 0x0004
|
||||
#define MADERA_AIF3TX3_ENA_MASK 0x0004
|
||||
#define MADERA_AIF3TX3_ENA_SHIFT 2
|
||||
#define MADERA_AIF3TX3_ENA_WIDTH 1
|
||||
#define MADERA_AIF3TX2_ENA 0x0002
|
||||
#define MADERA_AIF3TX2_ENA_MASK 0x0002
|
||||
#define MADERA_AIF3TX2_ENA_SHIFT 1
|
||||
@@ -2839,6 +2912,30 @@
|
||||
#define MADERA_AIF3TX1_ENA_WIDTH 1
|
||||
|
||||
/* (0x059A) AIF3_Rx_Enables */
|
||||
#define MADERA_AIF3RX8_ENA 0x0080
|
||||
#define MADERA_AIF3RX8_ENA_MASK 0x0080
|
||||
#define MADERA_AIF3RX8_ENA_SHIFT 7
|
||||
#define MADERA_AIF3RX8_ENA_WIDTH 1
|
||||
#define MADERA_AIF3RX7_ENA 0x0040
|
||||
#define MADERA_AIF3RX7_ENA_MASK 0x0040
|
||||
#define MADERA_AIF3RX7_ENA_SHIFT 6
|
||||
#define MADERA_AIF3RX7_ENA_WIDTH 1
|
||||
#define MADERA_AIF3RX6_ENA 0x0020
|
||||
#define MADERA_AIF3RX6_ENA_MASK 0x0020
|
||||
#define MADERA_AIF3RX6_ENA_SHIFT 5
|
||||
#define MADERA_AIF3RX6_ENA_WIDTH 1
|
||||
#define MADERA_AIF3RX5_ENA 0x0010
|
||||
#define MADERA_AIF3RX5_ENA_MASK 0x0010
|
||||
#define MADERA_AIF3RX5_ENA_SHIFT 4
|
||||
#define MADERA_AIF3RX5_ENA_WIDTH 1
|
||||
#define MADERA_AIF3RX4_ENA 0x0008
|
||||
#define MADERA_AIF3RX4_ENA_MASK 0x0008
|
||||
#define MADERA_AIF3RX4_ENA_SHIFT 3
|
||||
#define MADERA_AIF3RX4_ENA_WIDTH 1
|
||||
#define MADERA_AIF3RX3_ENA 0x0004
|
||||
#define MADERA_AIF3RX3_ENA_MASK 0x0004
|
||||
#define MADERA_AIF3RX3_ENA_SHIFT 2
|
||||
#define MADERA_AIF3RX3_ENA_WIDTH 1
|
||||
#define MADERA_AIF3RX2_ENA 0x0002
|
||||
#define MADERA_AIF3RX2_ENA_MASK 0x0002
|
||||
#define MADERA_AIF3RX2_ENA_SHIFT 1
|
||||
@@ -3453,6 +3550,25 @@
|
||||
#define MADERA_FCR_MIC_MODE_SEL_SHIFT 2
|
||||
#define MADERA_FCR_MIC_MODE_SEL_WIDTH 2
|
||||
|
||||
/* (0x10C0) AUXPDM1_CTRL_0 */
|
||||
#define MADERA_AUXPDM1_SRC_MASK 0x0F00
|
||||
#define MADERA_AUXPDM1_SRC_SHIFT 8
|
||||
#define MADERA_AUXPDM1_SRC_WIDTH 4
|
||||
#define MADERA_AUXPDM1_TXEDGE_MASK 0x0010
|
||||
#define MADERA_AUXPDM1_TXEDGE_SHIFT 4
|
||||
#define MADERA_AUXPDM1_TXEDGE_WIDTH 1
|
||||
#define MADERA_AUXPDM1_MSTR_MASK 0x0008
|
||||
#define MADERA_AUXPDM1_MSTR_SHIFT 3
|
||||
#define MADERA_AUXPDM1_MSTR_WIDTH 1
|
||||
#define MADERA_AUXPDM1_ENABLE_MASK 0x0001
|
||||
#define MADERA_AUXPDM1_ENABLE_SHIFT 0
|
||||
#define MADERA_AUXPDM1_ENABLE_WIDTH 1
|
||||
|
||||
/* (0x10C1) AUXPDM1_CTRL_1 */
|
||||
#define MADERA_AUXPDM1_CLK_FREQ_MASK 0xC000
|
||||
#define MADERA_AUXPDM1_CLK_FREQ_SHIFT 14
|
||||
#define MADERA_AUXPDM1_CLK_FREQ_WIDTH 2
|
||||
|
||||
/* (0x1480) DFC1_CTRL_W0 */
|
||||
#define MADERA_DFC1_RATE_MASK 0x007C
|
||||
#define MADERA_DFC1_RATE_SHIFT 2
|
||||
|
||||
@@ -374,6 +374,7 @@ enum rk805_reg {
|
||||
#define SWITCH1_EN BIT(5)
|
||||
#define DEV_OFF_RST BIT(3)
|
||||
#define DEV_OFF BIT(0)
|
||||
#define RTC_STOP BIT(0)
|
||||
|
||||
#define VB_LO_ACT BIT(4)
|
||||
#define VB_LO_SEL_3500MV (7 << 0)
|
||||
@@ -387,7 +388,179 @@ enum rk805_reg {
|
||||
#define SHUTDOWN_FUN (0x2 << 2)
|
||||
#define SLEEP_FUN (0x1 << 2)
|
||||
#define RK8XX_ID_MSK 0xfff0
|
||||
#define PWM_MODE_MSK BIT(7)
|
||||
#define FPWM_MODE BIT(7)
|
||||
#define AUTO_PWM_MODE 0
|
||||
|
||||
enum rk817_reg_id {
|
||||
RK817_ID_DCDC1 = 0,
|
||||
RK817_ID_DCDC2,
|
||||
RK817_ID_DCDC3,
|
||||
RK817_ID_DCDC4,
|
||||
RK817_ID_LDO1,
|
||||
RK817_ID_LDO2,
|
||||
RK817_ID_LDO3,
|
||||
RK817_ID_LDO4,
|
||||
RK817_ID_LDO5,
|
||||
RK817_ID_LDO6,
|
||||
RK817_ID_LDO7,
|
||||
RK817_ID_LDO8,
|
||||
RK817_ID_LDO9,
|
||||
RK817_ID_BOOST,
|
||||
RK817_ID_BOOST_OTG_SW,
|
||||
RK817_NUM_REGULATORS
|
||||
};
|
||||
|
||||
enum rk809_reg_id {
|
||||
RK809_ID_DCDC5 = RK817_ID_BOOST,
|
||||
RK809_ID_SW1,
|
||||
RK809_ID_SW2,
|
||||
RK809_NUM_REGULATORS
|
||||
};
|
||||
|
||||
#define RK817_SECONDS_REG 0x00
|
||||
#define RK817_MINUTES_REG 0x01
|
||||
#define RK817_HOURS_REG 0x02
|
||||
#define RK817_DAYS_REG 0x03
|
||||
#define RK817_MONTHS_REG 0x04
|
||||
#define RK817_YEARS_REG 0x05
|
||||
#define RK817_WEEKS_REG 0x06
|
||||
#define RK817_ALARM_SECONDS_REG 0x07
|
||||
#define RK817_ALARM_MINUTES_REG 0x08
|
||||
#define RK817_ALARM_HOURS_REG 0x09
|
||||
#define RK817_ALARM_DAYS_REG 0x0a
|
||||
#define RK817_ALARM_MONTHS_REG 0x0b
|
||||
#define RK817_ALARM_YEARS_REG 0x0c
|
||||
#define RK817_RTC_CTRL_REG 0xd
|
||||
#define RK817_RTC_STATUS_REG 0xe
|
||||
#define RK817_RTC_INT_REG 0xf
|
||||
#define RK817_RTC_COMP_LSB_REG 0x10
|
||||
#define RK817_RTC_COMP_MSB_REG 0x11
|
||||
|
||||
#define RK817_POWER_EN_REG(i) (0xb1 + (i))
|
||||
#define RK817_POWER_SLP_EN_REG(i) (0xb5 + (i))
|
||||
|
||||
#define RK817_POWER_CONFIG (0xb9)
|
||||
|
||||
#define RK817_BUCK_CONFIG_REG(i) (0xba + (i) * 3)
|
||||
|
||||
#define RK817_BUCK1_ON_VSEL_REG 0xBB
|
||||
#define RK817_BUCK1_SLP_VSEL_REG 0xBC
|
||||
|
||||
#define RK817_BUCK2_CONFIG_REG 0xBD
|
||||
#define RK817_BUCK2_ON_VSEL_REG 0xBE
|
||||
#define RK817_BUCK2_SLP_VSEL_REG 0xBF
|
||||
|
||||
#define RK817_BUCK3_CONFIG_REG 0xC0
|
||||
#define RK817_BUCK3_ON_VSEL_REG 0xC1
|
||||
#define RK817_BUCK3_SLP_VSEL_REG 0xC2
|
||||
|
||||
#define RK817_BUCK4_CONFIG_REG 0xC3
|
||||
#define RK817_BUCK4_ON_VSEL_REG 0xC4
|
||||
#define RK817_BUCK4_SLP_VSEL_REG 0xC5
|
||||
|
||||
#define RK817_LDO_ON_VSEL_REG(idx) (0xcc + (idx) * 2)
|
||||
#define RK817_BOOST_OTG_CFG (0xde)
|
||||
|
||||
#define RK817_ID_MSB 0xed
|
||||
#define RK817_ID_LSB 0xee
|
||||
|
||||
#define RK817_SYS_STS 0xf0
|
||||
#define RK817_SYS_CFG(i) (0xf1 + (i))
|
||||
|
||||
#define RK817_ON_SOURCE_REG 0xf5
|
||||
#define RK817_OFF_SOURCE_REG 0xf6
|
||||
|
||||
/* INTERRUPT REGISTER */
|
||||
#define RK817_INT_STS_REG0 0xf8
|
||||
#define RK817_INT_STS_MSK_REG0 0xf9
|
||||
#define RK817_INT_STS_REG1 0xfa
|
||||
#define RK817_INT_STS_MSK_REG1 0xfb
|
||||
#define RK817_INT_STS_REG2 0xfc
|
||||
#define RK817_INT_STS_MSK_REG2 0xfd
|
||||
#define RK817_GPIO_INT_CFG 0xfe
|
||||
|
||||
/* IRQ Definitions */
|
||||
#define RK817_IRQ_PWRON_FALL 0
|
||||
#define RK817_IRQ_PWRON_RISE 1
|
||||
#define RK817_IRQ_PWRON 2
|
||||
#define RK817_IRQ_PWMON_LP 3
|
||||
#define RK817_IRQ_HOTDIE 4
|
||||
#define RK817_IRQ_RTC_ALARM 5
|
||||
#define RK817_IRQ_RTC_PERIOD 6
|
||||
#define RK817_IRQ_VB_LO 7
|
||||
#define RK817_IRQ_PLUG_IN 8
|
||||
#define RK817_IRQ_PLUG_OUT 9
|
||||
#define RK817_IRQ_CHRG_TERM 10
|
||||
#define RK817_IRQ_CHRG_TIME 11
|
||||
#define RK817_IRQ_CHRG_TS 12
|
||||
#define RK817_IRQ_USB_OV 13
|
||||
#define RK817_IRQ_CHRG_IN_CLMP 14
|
||||
#define RK817_IRQ_BAT_DIS_ILIM 15
|
||||
#define RK817_IRQ_GATE_GPIO 16
|
||||
#define RK817_IRQ_TS_GPIO 17
|
||||
#define RK817_IRQ_CODEC_PD 18
|
||||
#define RK817_IRQ_CODEC_PO 19
|
||||
#define RK817_IRQ_CLASSD_MUTE_DONE 20
|
||||
#define RK817_IRQ_CLASSD_OCP 21
|
||||
#define RK817_IRQ_BAT_OVP 22
|
||||
#define RK817_IRQ_CHRG_BAT_HI 23
|
||||
#define RK817_IRQ_END (RK817_IRQ_CHRG_BAT_HI + 1)
|
||||
|
||||
/*
|
||||
* rtc_ctrl 0xd
|
||||
* same as 808, except bit4
|
||||
*/
|
||||
#define RK817_RTC_CTRL_RSV4 BIT(4)
|
||||
|
||||
/* power config 0xb9 */
|
||||
#define RK817_BUCK3_FB_RES_MSK BIT(6)
|
||||
#define RK817_BUCK3_FB_RES_INTER BIT(6)
|
||||
#define RK817_BUCK3_FB_RES_EXT 0
|
||||
|
||||
/* buck config 0xba */
|
||||
#define RK817_RAMP_RATE_OFFSET 6
|
||||
#define RK817_RAMP_RATE_MASK (0x3 << RK817_RAMP_RATE_OFFSET)
|
||||
#define RK817_RAMP_RATE_3MV_PER_US (0x0 << RK817_RAMP_RATE_OFFSET)
|
||||
#define RK817_RAMP_RATE_6_3MV_PER_US (0x1 << RK817_RAMP_RATE_OFFSET)
|
||||
#define RK817_RAMP_RATE_12_5MV_PER_US (0x2 << RK817_RAMP_RATE_OFFSET)
|
||||
#define RK817_RAMP_RATE_25MV_PER_US (0x3 << RK817_RAMP_RATE_OFFSET)
|
||||
|
||||
/* sys_cfg1 0xf2 */
|
||||
#define RK817_HOTDIE_TEMP_MSK (0x3 << 4)
|
||||
#define RK817_HOTDIE_85 (0x0 << 4)
|
||||
#define RK817_HOTDIE_95 (0x1 << 4)
|
||||
#define RK817_HOTDIE_105 (0x2 << 4)
|
||||
#define RK817_HOTDIE_115 (0x3 << 4)
|
||||
|
||||
#define RK817_TSD_TEMP_MSK BIT(6)
|
||||
#define RK817_TSD_140 0
|
||||
#define RK817_TSD_160 BIT(6)
|
||||
|
||||
#define RK817_CLK32KOUT2_EN BIT(7)
|
||||
|
||||
/* sys_cfg3 0xf4 */
|
||||
#define RK817_SLPPIN_FUNC_MSK (0x3 << 3)
|
||||
#define SLPPIN_NULL_FUN (0x0 << 3)
|
||||
#define SLPPIN_SLP_FUN (0x1 << 3)
|
||||
#define SLPPIN_DN_FUN (0x2 << 3)
|
||||
#define SLPPIN_RST_FUN (0x3 << 3)
|
||||
|
||||
#define RK817_RST_FUNC_MSK (0x3 << 6)
|
||||
#define RK817_RST_FUNC_SFT (6)
|
||||
#define RK817_RST_FUNC_CNT (3)
|
||||
#define RK817_RST_FUNC_DEV (0) /* reset the dev */
|
||||
#define RK817_RST_FUNC_REG (0x1 << 6) /* reset the reg only */
|
||||
|
||||
#define RK817_SLPPOL_MSK BIT(5)
|
||||
#define RK817_SLPPOL_H BIT(5)
|
||||
#define RK817_SLPPOL_L (0)
|
||||
|
||||
/* gpio&int 0xfe */
|
||||
#define RK817_INT_POL_MSK BIT(1)
|
||||
#define RK817_INT_POL_H BIT(1)
|
||||
#define RK817_INT_POL_L 0
|
||||
#define RK809_BUCK5_CONFIG(i) (RK817_BOOST_OTG_CFG + (i) * 1)
|
||||
|
||||
enum {
|
||||
BUCK_ILMIN_50MA,
|
||||
@@ -435,6 +608,8 @@ enum {
|
||||
enum {
|
||||
RK805_ID = 0x8050,
|
||||
RK808_ID = 0x0000,
|
||||
RK809_ID = 0x8090,
|
||||
RK817_ID = 0x8170,
|
||||
RK818_ID = 0x8181,
|
||||
};
|
||||
|
||||
@@ -445,5 +620,7 @@ struct rk808 {
|
||||
long variant;
|
||||
const struct regmap_config *regmap_cfg;
|
||||
const struct regmap_irq_chip *regmap_irq_chip;
|
||||
void (*pm_pwroff_fn)(void);
|
||||
void (*pm_pwroff_prep_fn)(void);
|
||||
};
|
||||
#endif /* __LINUX_REGULATOR_RK808_H */
|
||||
|
||||
408
include/linux/mfd/rohm-bd70528.h
Normal file
408
include/linux/mfd/rohm-bd70528.h
Normal file
@@ -0,0 +1,408 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/* Copyright (C) 2018 ROHM Semiconductors */
|
||||
|
||||
#ifndef __LINUX_MFD_BD70528_H__
|
||||
#define __LINUX_MFD_BD70528_H__
|
||||
|
||||
#include <linux/bits.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/mfd/rohm-generic.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
enum {
|
||||
BD70528_BUCK1,
|
||||
BD70528_BUCK2,
|
||||
BD70528_BUCK3,
|
||||
BD70528_LDO1,
|
||||
BD70528_LDO2,
|
||||
BD70528_LDO3,
|
||||
BD70528_LED1,
|
||||
BD70528_LED2,
|
||||
};
|
||||
|
||||
struct bd70528_data {
|
||||
struct rohm_regmap_dev chip;
|
||||
struct mutex rtc_timer_lock;
|
||||
};
|
||||
|
||||
#define BD70528_BUCK_VOLTS 17
|
||||
#define BD70528_BUCK_VOLTS 17
|
||||
#define BD70528_BUCK_VOLTS 17
|
||||
#define BD70528_LDO_VOLTS 0x20
|
||||
|
||||
#define BD70528_REG_BUCK1_EN 0x0F
|
||||
#define BD70528_REG_BUCK1_VOLT 0x15
|
||||
#define BD70528_REG_BUCK2_EN 0x10
|
||||
#define BD70528_REG_BUCK2_VOLT 0x16
|
||||
#define BD70528_REG_BUCK3_EN 0x11
|
||||
#define BD70528_REG_BUCK3_VOLT 0x17
|
||||
#define BD70528_REG_LDO1_EN 0x1b
|
||||
#define BD70528_REG_LDO1_VOLT 0x1e
|
||||
#define BD70528_REG_LDO2_EN 0x1c
|
||||
#define BD70528_REG_LDO2_VOLT 0x1f
|
||||
#define BD70528_REG_LDO3_EN 0x1d
|
||||
#define BD70528_REG_LDO3_VOLT 0x20
|
||||
#define BD70528_REG_LED_CTRL 0x2b
|
||||
#define BD70528_REG_LED_VOLT 0x29
|
||||
#define BD70528_REG_LED_EN 0x2a
|
||||
|
||||
/* main irq registers */
|
||||
#define BD70528_REG_INT_MAIN 0x7E
|
||||
#define BD70528_REG_INT_MAIN_MASK 0x74
|
||||
|
||||
/* 'sub irq' registers */
|
||||
#define BD70528_REG_INT_SHDN 0x7F
|
||||
#define BD70528_REG_INT_PWR_FLT 0x80
|
||||
#define BD70528_REG_INT_VR_FLT 0x81
|
||||
#define BD70528_REG_INT_MISC 0x82
|
||||
#define BD70528_REG_INT_BAT1 0x83
|
||||
#define BD70528_REG_INT_BAT2 0x84
|
||||
#define BD70528_REG_INT_RTC 0x85
|
||||
#define BD70528_REG_INT_GPIO 0x86
|
||||
#define BD70528_REG_INT_OP_FAIL 0x87
|
||||
|
||||
#define BD70528_REG_INT_SHDN_MASK 0x75
|
||||
#define BD70528_REG_INT_PWR_FLT_MASK 0x76
|
||||
#define BD70528_REG_INT_VR_FLT_MASK 0x77
|
||||
#define BD70528_REG_INT_MISC_MASK 0x78
|
||||
#define BD70528_REG_INT_BAT1_MASK 0x79
|
||||
#define BD70528_REG_INT_BAT2_MASK 0x7a
|
||||
#define BD70528_REG_INT_RTC_MASK 0x7b
|
||||
#define BD70528_REG_INT_GPIO_MASK 0x7c
|
||||
#define BD70528_REG_INT_OP_FAIL_MASK 0x7d
|
||||
|
||||
/* Reset related 'magic' registers */
|
||||
#define BD70528_REG_SHIPMODE 0x03
|
||||
#define BD70528_REG_HWRESET 0x04
|
||||
#define BD70528_REG_WARMRESET 0x05
|
||||
#define BD70528_REG_STANDBY 0x06
|
||||
|
||||
/* GPIO registers */
|
||||
#define BD70528_REG_GPIO_STATE 0x8F
|
||||
|
||||
#define BD70528_REG_GPIO1_IN 0x4d
|
||||
#define BD70528_REG_GPIO2_IN 0x4f
|
||||
#define BD70528_REG_GPIO3_IN 0x51
|
||||
#define BD70528_REG_GPIO4_IN 0x53
|
||||
#define BD70528_REG_GPIO1_OUT 0x4e
|
||||
#define BD70528_REG_GPIO2_OUT 0x50
|
||||
#define BD70528_REG_GPIO3_OUT 0x52
|
||||
#define BD70528_REG_GPIO4_OUT 0x54
|
||||
|
||||
/* clk control */
|
||||
|
||||
#define BD70528_REG_CLK_OUT 0x2c
|
||||
|
||||
/* RTC */
|
||||
|
||||
#define BD70528_REG_RTC_COUNT_H 0x2d
|
||||
#define BD70528_REG_RTC_COUNT_L 0x2e
|
||||
#define BD70528_REG_RTC_SEC 0x2f
|
||||
#define BD70528_REG_RTC_MINUTE 0x30
|
||||
#define BD70528_REG_RTC_HOUR 0x31
|
||||
#define BD70528_REG_RTC_WEEK 0x32
|
||||
#define BD70528_REG_RTC_DAY 0x33
|
||||
#define BD70528_REG_RTC_MONTH 0x34
|
||||
#define BD70528_REG_RTC_YEAR 0x35
|
||||
|
||||
#define BD70528_REG_RTC_ALM_SEC 0x36
|
||||
#define BD70528_REG_RTC_ALM_START BD70528_REG_RTC_ALM_SEC
|
||||
#define BD70528_REG_RTC_ALM_MINUTE 0x37
|
||||
#define BD70528_REG_RTC_ALM_HOUR 0x38
|
||||
#define BD70528_REG_RTC_ALM_WEEK 0x39
|
||||
#define BD70528_REG_RTC_ALM_DAY 0x3a
|
||||
#define BD70528_REG_RTC_ALM_MONTH 0x3b
|
||||
#define BD70528_REG_RTC_ALM_YEAR 0x3c
|
||||
#define BD70528_REG_RTC_ALM_MASK 0x3d
|
||||
#define BD70528_REG_RTC_ALM_REPEAT 0x3e
|
||||
#define BD70528_REG_RTC_START BD70528_REG_RTC_SEC
|
||||
|
||||
#define BD70528_REG_RTC_WAKE_SEC 0x43
|
||||
#define BD70528_REG_RTC_WAKE_START BD70528_REG_RTC_WAKE_SEC
|
||||
#define BD70528_REG_RTC_WAKE_MIN 0x44
|
||||
#define BD70528_REG_RTC_WAKE_HOUR 0x45
|
||||
#define BD70528_REG_RTC_WAKE_CTRL 0x46
|
||||
|
||||
#define BD70528_REG_ELAPSED_TIMER_EN 0x42
|
||||
#define BD70528_REG_WAKE_EN 0x46
|
||||
|
||||
/* WDT registers */
|
||||
#define BD70528_REG_WDT_CTRL 0x4A
|
||||
#define BD70528_REG_WDT_HOUR 0x49
|
||||
#define BD70528_REG_WDT_MINUTE 0x48
|
||||
#define BD70528_REG_WDT_SEC 0x47
|
||||
|
||||
/* Charger / Battery */
|
||||
#define BD70528_REG_CHG_CURR_STAT 0x59
|
||||
#define BD70528_REG_CHG_BAT_STAT 0x57
|
||||
#define BD70528_REG_CHG_BAT_TEMP 0x58
|
||||
#define BD70528_REG_CHG_IN_STAT 0x56
|
||||
#define BD70528_REG_CHG_DCIN_ILIM 0x5d
|
||||
#define BD70528_REG_CHG_CHG_CURR_WARM 0x61
|
||||
#define BD70528_REG_CHG_CHG_CURR_COLD 0x62
|
||||
|
||||
/* Masks for main IRQ register bits */
|
||||
enum {
|
||||
BD70528_INT_SHDN,
|
||||
#define BD70528_INT_SHDN_MASK BIT(BD70528_INT_SHDN)
|
||||
BD70528_INT_PWR_FLT,
|
||||
#define BD70528_INT_PWR_FLT_MASK BIT(BD70528_INT_PWR_FLT)
|
||||
BD70528_INT_VR_FLT,
|
||||
#define BD70528_INT_VR_FLT_MASK BIT(BD70528_INT_VR_FLT)
|
||||
BD70528_INT_MISC,
|
||||
#define BD70528_INT_MISC_MASK BIT(BD70528_INT_MISC)
|
||||
BD70528_INT_BAT1,
|
||||
#define BD70528_INT_BAT1_MASK BIT(BD70528_INT_BAT1)
|
||||
BD70528_INT_RTC,
|
||||
#define BD70528_INT_RTC_MASK BIT(BD70528_INT_RTC)
|
||||
BD70528_INT_GPIO,
|
||||
#define BD70528_INT_GPIO_MASK BIT(BD70528_INT_GPIO)
|
||||
BD70528_INT_OP_FAIL,
|
||||
#define BD70528_INT_OP_FAIL_MASK BIT(BD70528_INT_OP_FAIL)
|
||||
};
|
||||
|
||||
/* IRQs */
|
||||
enum {
|
||||
/* Shutdown register IRQs */
|
||||
BD70528_INT_LONGPUSH,
|
||||
BD70528_INT_WDT,
|
||||
BD70528_INT_HWRESET,
|
||||
BD70528_INT_RSTB_FAULT,
|
||||
BD70528_INT_VBAT_UVLO,
|
||||
BD70528_INT_TSD,
|
||||
BD70528_INT_RSTIN,
|
||||
/* Power failure register IRQs */
|
||||
BD70528_INT_BUCK1_FAULT,
|
||||
BD70528_INT_BUCK2_FAULT,
|
||||
BD70528_INT_BUCK3_FAULT,
|
||||
BD70528_INT_LDO1_FAULT,
|
||||
BD70528_INT_LDO2_FAULT,
|
||||
BD70528_INT_LDO3_FAULT,
|
||||
BD70528_INT_LED1_FAULT,
|
||||
BD70528_INT_LED2_FAULT,
|
||||
/* VR FAULT register IRQs */
|
||||
BD70528_INT_BUCK1_OCP,
|
||||
BD70528_INT_BUCK2_OCP,
|
||||
BD70528_INT_BUCK3_OCP,
|
||||
BD70528_INT_LED1_OCP,
|
||||
BD70528_INT_LED2_OCP,
|
||||
BD70528_INT_BUCK1_FULLON,
|
||||
BD70528_INT_BUCK2_FULLON,
|
||||
/* PMU register interrupts */
|
||||
BD70528_INT_SHORTPUSH,
|
||||
BD70528_INT_AUTO_WAKEUP,
|
||||
BD70528_INT_STATE_CHANGE,
|
||||
/* Charger 1 register IRQs */
|
||||
BD70528_INT_BAT_OV_RES,
|
||||
BD70528_INT_BAT_OV_DET,
|
||||
BD70528_INT_DBAT_DET,
|
||||
BD70528_INT_BATTSD_COLD_RES,
|
||||
BD70528_INT_BATTSD_COLD_DET,
|
||||
BD70528_INT_BATTSD_HOT_RES,
|
||||
BD70528_INT_BATTSD_HOT_DET,
|
||||
BD70528_INT_CHG_TSD,
|
||||
/* Charger 2 register IRQs */
|
||||
BD70528_INT_BAT_RMV,
|
||||
BD70528_INT_BAT_DET,
|
||||
BD70528_INT_DCIN2_OV_RES,
|
||||
BD70528_INT_DCIN2_OV_DET,
|
||||
BD70528_INT_DCIN2_RMV,
|
||||
BD70528_INT_DCIN2_DET,
|
||||
BD70528_INT_DCIN1_RMV,
|
||||
BD70528_INT_DCIN1_DET,
|
||||
/* RTC register IRQs */
|
||||
BD70528_INT_RTC_ALARM,
|
||||
BD70528_INT_ELPS_TIM,
|
||||
/* GPIO register IRQs */
|
||||
BD70528_INT_GPIO0,
|
||||
BD70528_INT_GPIO1,
|
||||
BD70528_INT_GPIO2,
|
||||
BD70528_INT_GPIO3,
|
||||
/* Invalid operation register IRQs */
|
||||
BD70528_INT_BUCK1_DVS_OPFAIL,
|
||||
BD70528_INT_BUCK2_DVS_OPFAIL,
|
||||
BD70528_INT_BUCK3_DVS_OPFAIL,
|
||||
BD70528_INT_LED1_VOLT_OPFAIL,
|
||||
BD70528_INT_LED2_VOLT_OPFAIL,
|
||||
};
|
||||
|
||||
/* Masks */
|
||||
#define BD70528_INT_LONGPUSH_MASK 0x1
|
||||
#define BD70528_INT_WDT_MASK 0x2
|
||||
#define BD70528_INT_HWRESET_MASK 0x4
|
||||
#define BD70528_INT_RSTB_FAULT_MASK 0x8
|
||||
#define BD70528_INT_VBAT_UVLO_MASK 0x10
|
||||
#define BD70528_INT_TSD_MASK 0x20
|
||||
#define BD70528_INT_RSTIN_MASK 0x40
|
||||
|
||||
#define BD70528_INT_BUCK1_FAULT_MASK 0x1
|
||||
#define BD70528_INT_BUCK2_FAULT_MASK 0x2
|
||||
#define BD70528_INT_BUCK3_FAULT_MASK 0x4
|
||||
#define BD70528_INT_LDO1_FAULT_MASK 0x8
|
||||
#define BD70528_INT_LDO2_FAULT_MASK 0x10
|
||||
#define BD70528_INT_LDO3_FAULT_MASK 0x20
|
||||
#define BD70528_INT_LED1_FAULT_MASK 0x40
|
||||
#define BD70528_INT_LED2_FAULT_MASK 0x80
|
||||
|
||||
#define BD70528_INT_BUCK1_OCP_MASK 0x1
|
||||
#define BD70528_INT_BUCK2_OCP_MASK 0x2
|
||||
#define BD70528_INT_BUCK3_OCP_MASK 0x4
|
||||
#define BD70528_INT_LED1_OCP_MASK 0x8
|
||||
#define BD70528_INT_LED2_OCP_MASK 0x10
|
||||
#define BD70528_INT_BUCK1_FULLON_MASK 0x20
|
||||
#define BD70528_INT_BUCK2_FULLON_MASK 0x40
|
||||
|
||||
#define BD70528_INT_SHORTPUSH_MASK 0x1
|
||||
#define BD70528_INT_AUTO_WAKEUP_MASK 0x2
|
||||
#define BD70528_INT_STATE_CHANGE_MASK 0x10
|
||||
|
||||
#define BD70528_INT_BAT_OV_RES_MASK 0x1
|
||||
#define BD70528_INT_BAT_OV_DET_MASK 0x2
|
||||
#define BD70528_INT_DBAT_DET_MASK 0x4
|
||||
#define BD70528_INT_BATTSD_COLD_RES_MASK 0x8
|
||||
#define BD70528_INT_BATTSD_COLD_DET_MASK 0x10
|
||||
#define BD70528_INT_BATTSD_HOT_RES_MASK 0x20
|
||||
#define BD70528_INT_BATTSD_HOT_DET_MASK 0x40
|
||||
#define BD70528_INT_CHG_TSD_MASK 0x80
|
||||
|
||||
#define BD70528_INT_BAT_RMV_MASK 0x1
|
||||
#define BD70528_INT_BAT_DET_MASK 0x2
|
||||
#define BD70528_INT_DCIN2_OV_RES_MASK 0x4
|
||||
#define BD70528_INT_DCIN2_OV_DET_MASK 0x8
|
||||
#define BD70528_INT_DCIN2_RMV_MASK 0x10
|
||||
#define BD70528_INT_DCIN2_DET_MASK 0x20
|
||||
#define BD70528_INT_DCIN1_RMV_MASK 0x40
|
||||
#define BD70528_INT_DCIN1_DET_MASK 0x80
|
||||
|
||||
#define BD70528_INT_RTC_ALARM_MASK 0x1
|
||||
#define BD70528_INT_ELPS_TIM_MASK 0x2
|
||||
|
||||
#define BD70528_INT_GPIO0_MASK 0x1
|
||||
#define BD70528_INT_GPIO1_MASK 0x2
|
||||
#define BD70528_INT_GPIO2_MASK 0x4
|
||||
#define BD70528_INT_GPIO3_MASK 0x8
|
||||
|
||||
#define BD70528_INT_BUCK1_DVS_OPFAIL_MASK 0x1
|
||||
#define BD70528_INT_BUCK2_DVS_OPFAIL_MASK 0x2
|
||||
#define BD70528_INT_BUCK3_DVS_OPFAIL_MASK 0x4
|
||||
#define BD70528_INT_LED1_VOLT_OPFAIL_MASK 0x10
|
||||
#define BD70528_INT_LED2_VOLT_OPFAIL_MASK 0x20
|
||||
|
||||
#define BD70528_DEBOUNCE_MASK 0x3
|
||||
|
||||
#define BD70528_DEBOUNCE_DISABLE 0
|
||||
#define BD70528_DEBOUNCE_15MS 1
|
||||
#define BD70528_DEBOUNCE_30MS 2
|
||||
#define BD70528_DEBOUNCE_50MS 3
|
||||
|
||||
#define BD70528_GPIO_DRIVE_MASK 0x2
|
||||
#define BD70528_GPIO_PUSH_PULL 0x0
|
||||
#define BD70528_GPIO_OPEN_DRAIN 0x2
|
||||
|
||||
#define BD70528_GPIO_OUT_EN_MASK 0x80
|
||||
#define BD70528_GPIO_OUT_ENABLE 0x80
|
||||
#define BD70528_GPIO_OUT_DISABLE 0x0
|
||||
|
||||
#define BD70528_GPIO_OUT_HI 0x1
|
||||
#define BD70528_GPIO_OUT_LO 0x0
|
||||
#define BD70528_GPIO_OUT_MASK 0x1
|
||||
|
||||
#define BD70528_GPIO_IN_STATE_BASE 1
|
||||
|
||||
#define BD70528_CLK_OUT_EN_MASK 0x1
|
||||
|
||||
/* RTC masks to mask out reserved bits */
|
||||
|
||||
#define BD70528_MASK_RTC_SEC 0x7f
|
||||
#define BD70528_MASK_RTC_MINUTE 0x7f
|
||||
#define BD70528_MASK_RTC_HOUR_24H 0x80
|
||||
#define BD70528_MASK_RTC_HOUR_PM 0x20
|
||||
#define BD70528_MASK_RTC_HOUR 0x1f
|
||||
#define BD70528_MASK_RTC_DAY 0x3f
|
||||
#define BD70528_MASK_RTC_WEEK 0x07
|
||||
#define BD70528_MASK_RTC_MONTH 0x1f
|
||||
#define BD70528_MASK_RTC_YEAR 0xff
|
||||
#define BD70528_MASK_RTC_COUNT_L 0x7f
|
||||
|
||||
#define BD70528_MASK_ELAPSED_TIMER_EN 0x1
|
||||
/* Mask second, min and hour fields
|
||||
* HW would support ALM irq for over 24h
|
||||
* (by setting day, month and year too)
|
||||
* but as we wish to keep this same as for
|
||||
* wake-up we limit ALM to 24H and only
|
||||
* unmask sec, min and hour
|
||||
*/
|
||||
#define BD70528_MASK_ALM_EN 0x7
|
||||
#define BD70528_MASK_WAKE_EN 0x1
|
||||
|
||||
/* WDT masks */
|
||||
#define BD70528_MASK_WDT_EN 0x1
|
||||
#define BD70528_MASK_WDT_HOUR 0x1
|
||||
#define BD70528_MASK_WDT_MINUTE 0x7f
|
||||
#define BD70528_MASK_WDT_SEC 0x7f
|
||||
|
||||
#define BD70528_WDT_STATE_BIT 0x1
|
||||
#define BD70528_ELAPSED_STATE_BIT 0x2
|
||||
#define BD70528_WAKE_STATE_BIT 0x4
|
||||
|
||||
/* Charger masks */
|
||||
#define BD70528_MASK_CHG_STAT 0x7f
|
||||
#define BD70528_MASK_CHG_BAT_TIMER 0x20
|
||||
#define BD70528_MASK_CHG_BAT_OVERVOLT 0x10
|
||||
#define BD70528_MASK_CHG_BAT_DETECT 0x1
|
||||
#define BD70528_MASK_CHG_DCIN1_UVLO 0x1
|
||||
#define BD70528_MASK_CHG_DCIN_ILIM 0x3f
|
||||
#define BD70528_MASK_CHG_CHG_CURR 0x1f
|
||||
#define BD70528_MASK_CHG_TRICKLE_CURR 0x10
|
||||
|
||||
/*
|
||||
* Note, external battery register is the lonely rider at
|
||||
* address 0xc5. See how to stuff that in the regmap
|
||||
*/
|
||||
#define BD70528_MAX_REGISTER 0x94
|
||||
|
||||
/* Buck control masks */
|
||||
#define BD70528_MASK_RUN_EN 0x4
|
||||
#define BD70528_MASK_STBY_EN 0x2
|
||||
#define BD70528_MASK_IDLE_EN 0x1
|
||||
#define BD70528_MASK_LED1_EN 0x1
|
||||
#define BD70528_MASK_LED2_EN 0x10
|
||||
|
||||
#define BD70528_MASK_BUCK_VOLT 0xf
|
||||
#define BD70528_MASK_LDO_VOLT 0x1f
|
||||
#define BD70528_MASK_LED1_VOLT 0x1
|
||||
#define BD70528_MASK_LED2_VOLT 0x10
|
||||
|
||||
/* Misc irq masks */
|
||||
#define BD70528_INT_MASK_SHORT_PUSH 1
|
||||
#define BD70528_INT_MASK_AUTO_WAKE 2
|
||||
#define BD70528_INT_MASK_POWER_STATE 4
|
||||
|
||||
#define BD70528_MASK_BUCK_RAMP 0x10
|
||||
#define BD70528_SIFT_BUCK_RAMP 4
|
||||
|
||||
#if IS_ENABLED(CONFIG_BD70528_WATCHDOG)
|
||||
|
||||
int bd70528_wdt_set(struct rohm_regmap_dev *data, int enable, int *old_state);
|
||||
void bd70528_wdt_lock(struct rohm_regmap_dev *data);
|
||||
void bd70528_wdt_unlock(struct rohm_regmap_dev *data);
|
||||
|
||||
#else /* CONFIG_BD70528_WATCHDOG */
|
||||
|
||||
static inline int bd70528_wdt_set(struct rohm_regmap_dev *data, int enable,
|
||||
int *old_state)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void bd70528_wdt_lock(struct rohm_regmap_dev *data)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void bd70528_wdt_unlock(struct rohm_regmap_dev *data)
|
||||
{
|
||||
}
|
||||
|
||||
#endif /* CONFIG_BD70528_WATCHDOG */
|
||||
|
||||
#endif /* __LINUX_MFD_BD70528_H__ */
|
||||
@@ -4,14 +4,9 @@
|
||||
#ifndef __LINUX_MFD_BD718XX_H__
|
||||
#define __LINUX_MFD_BD718XX_H__
|
||||
|
||||
#include <linux/mfd/rohm-generic.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
enum {
|
||||
BD718XX_TYPE_BD71837 = 0,
|
||||
BD718XX_TYPE_BD71847,
|
||||
BD718XX_TYPE_AMOUNT
|
||||
};
|
||||
|
||||
enum {
|
||||
BD718XX_BUCK1 = 0,
|
||||
BD718XX_BUCK2,
|
||||
@@ -321,18 +316,17 @@ enum {
|
||||
BD718XX_PWRBTN_LONG_PRESS_15S
|
||||
};
|
||||
|
||||
struct bd718xx_clk;
|
||||
|
||||
struct bd718xx {
|
||||
unsigned int chip_type;
|
||||
struct device *dev;
|
||||
struct regmap *regmap;
|
||||
unsigned long int id;
|
||||
/*
|
||||
* Please keep this as the first member here as some
|
||||
* drivers (clk) supporting more than one chip may only know this
|
||||
* generic struct 'struct rohm_regmap_dev' and assume it is
|
||||
* the first chunk of parent device's private data.
|
||||
*/
|
||||
struct rohm_regmap_dev chip;
|
||||
|
||||
int chip_irq;
|
||||
struct regmap_irq_chip_data *irq_data;
|
||||
|
||||
struct bd718xx_clk *clk;
|
||||
};
|
||||
|
||||
#endif /* __LINUX_MFD_BD718XX_H__ */
|
||||
|
||||
20
include/linux/mfd/rohm-generic.h
Normal file
20
include/linux/mfd/rohm-generic.h
Normal file
@@ -0,0 +1,20 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/* Copyright (C) 2018 ROHM Semiconductors */
|
||||
|
||||
#ifndef __LINUX_MFD_ROHM_H__
|
||||
#define __LINUX_MFD_ROHM_H__
|
||||
|
||||
enum {
|
||||
ROHM_CHIP_TYPE_BD71837 = 0,
|
||||
ROHM_CHIP_TYPE_BD71847,
|
||||
ROHM_CHIP_TYPE_BD70528,
|
||||
ROHM_CHIP_TYPE_AMOUNT
|
||||
};
|
||||
|
||||
struct rohm_regmap_dev {
|
||||
unsigned int chip_type;
|
||||
struct device *dev;
|
||||
struct regmap *regmap;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -5,7 +5,7 @@
|
||||
*/
|
||||
|
||||
#ifndef MFD_STMFX_H
|
||||
#define MFX_STMFX_H
|
||||
#define MFD_STMFX_H
|
||||
|
||||
#include <linux/regmap.h>
|
||||
|
||||
|
||||
Reference in New Issue
Block a user