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[MIPS] kgdb: Remove existing implementation

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This patch explicitly removes the kgdb implementation, for mips which
is intended to be followed by a patch that adds a kgdb implementation
for MIPS that makes use of the kgdb core in the kernel.

Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Jason Wessel
2008-07-29 15:58:52 -05:00
committed by Ralf Baechle
parent 8f8da9adeb
commit 8d60a903d9
59 changed files with 4 additions and 3134 deletions
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73
arch/mips/pmc-sierra/msp71xx/msp_serial.c
View File

@@ -38,68 +38,6 @@
#include <msp_int.h>
#include <msp_regs.h>
#ifdef CONFIG_KGDB
/*
* kgdb uses serial port 1 so the console can remain on port 0.
* To use port 0 change the definition to read as follows:
* #define DEBUG_PORT_BASE KSEG1ADDR(MSP_UART0_BASE)
*/
#define DEBUG_PORT_BASE KSEG1ADDR(MSP_UART1_BASE)
int putDebugChar(char c)
{
volatile uint32_t *uart = (volatile uint32_t *)DEBUG_PORT_BASE;
uint32_t val = (uint32_t)c;
local_irq_disable();
while( !(uart[5] & 0x20) ); /* Wait for TXRDY */
uart[0] = val;
while( !(uart[5] & 0x20) ); /* Wait for TXRDY */
local_irq_enable();
return 1;
}
char getDebugChar(void)
{
volatile uint32_t *uart = (volatile uint32_t *)DEBUG_PORT_BASE;
uint32_t val;
while( !(uart[5] & 0x01) ); /* Wait for RXRDY */
val = uart[0];
return (char)val;
}
void initDebugPort(unsigned int uartclk, unsigned int baudrate)
{
unsigned int baud_divisor = (uartclk + 8 * baudrate)/(16 * baudrate);
/* Enable FIFOs */
writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_4,
(char *)DEBUG_PORT_BASE + (UART_FCR * 4));
/* Select brtc divisor */
writeb(UART_LCR_DLAB, (char *)DEBUG_PORT_BASE + (UART_LCR * 4));
/* Store divisor lsb */
writeb(baud_divisor, (char *)DEBUG_PORT_BASE + (UART_TX * 4));
/* Store divisor msb */
writeb(baud_divisor >> 8, (char *)DEBUG_PORT_BASE + (UART_IER * 4));
/* Set 8N1 mode */
writeb(UART_LCR_WLEN8, (char *)DEBUG_PORT_BASE + (UART_LCR * 4));
/* Disable flow control */
writeb(0, (char *)DEBUG_PORT_BASE + (UART_MCR * 4));
/* Disable receive interrupt(!) */
writeb(0, (char *)DEBUG_PORT_BASE + (UART_IER * 4));
}
#endif
void __init msp_serial_setup(void)
{
char *s;
@@ -139,17 +77,6 @@ void __init msp_serial_setup(void)
case MACH_MSP7120_FPGA:
/* Enable UART1 on MSP4200 and MSP7120 */
*GPIO_CFG2_REG = 0x00002299;
#ifdef CONFIG_KGDB
/* Initialize UART1 for kgdb since PMON doesn't */
if( DEBUG_PORT_BASE == KSEG1ADDR(MSP_UART1_BASE) ) {
if( mips_machtype == MACH_MSP4200_FPGA
|| mips_machtype == MACH_MSP7120_FPGA )
initDebugPort(uartclk, 19200);
else
initDebugPort(uartclk, 57600);
}
#endif
break;
default:

1
arch/mips/pmc-sierra/yosemite/Makefile
View File

@@ -4,7 +4,6 @@
obj-y += irq.o prom.o py-console.o setup.o
obj-$(CONFIG_KGDB) += dbg_io.o
obj-$(CONFIG_SMP) += smp.o
EXTRA_CFLAGS += -Werror

180
arch/mips/pmc-sierra/yosemite/dbg_io.c
View File

@@ -1,180 +0,0 @@
/*
* Copyright 2003 PMC-Sierra
* Author: Manish Lachwani (lachwani@pmc-sierra.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
* Support for KGDB for the Yosemite board. We make use of single serial
* port to be used for KGDB as well as console. The second serial port
* seems to be having a problem. Single IRQ is allocated for both the
* ports. Hence, the interrupt routing code needs to figure out whether
* the interrupt came from channel A or B.
*/
#include <asm/serial.h>
/*
* Baud rate, Parity, Data and Stop bit settings for the
* serial port on the Yosemite. Note that the Early printk
* patch has been added. So, we should be all set to go
*/
#define YOSEMITE_BAUD_2400 2400
#define YOSEMITE_BAUD_4800 4800
#define YOSEMITE_BAUD_9600 9600
#define YOSEMITE_BAUD_19200 19200
#define YOSEMITE_BAUD_38400 38400
#define YOSEMITE_BAUD_57600 57600
#define YOSEMITE_BAUD_115200 115200
#define YOSEMITE_PARITY_NONE 0
#define YOSEMITE_PARITY_ODD 0x08
#define YOSEMITE_PARITY_EVEN 0x18
#define YOSEMITE_PARITY_MARK 0x28
#define YOSEMITE_PARITY_SPACE 0x38
#define YOSEMITE_DATA_5BIT 0x0
#define YOSEMITE_DATA_6BIT 0x1
#define YOSEMITE_DATA_7BIT 0x2
#define YOSEMITE_DATA_8BIT 0x3
#define YOSEMITE_STOP_1BIT 0x0
#define YOSEMITE_STOP_2BIT 0x4
/* This is crucial */
#define SERIAL_REG_OFS 0x1
#define SERIAL_RCV_BUFFER 0x0
#define SERIAL_TRANS_HOLD 0x0
#define SERIAL_SEND_BUFFER 0x0
#define SERIAL_INTR_ENABLE (1 * SERIAL_REG_OFS)
#define SERIAL_INTR_ID (2 * SERIAL_REG_OFS)
#define SERIAL_DATA_FORMAT (3 * SERIAL_REG_OFS)
#define SERIAL_LINE_CONTROL (3 * SERIAL_REG_OFS)
#define SERIAL_MODEM_CONTROL (4 * SERIAL_REG_OFS)
#define SERIAL_RS232_OUTPUT (4 * SERIAL_REG_OFS)
#define SERIAL_LINE_STATUS (5 * SERIAL_REG_OFS)
#define SERIAL_MODEM_STATUS (6 * SERIAL_REG_OFS)
#define SERIAL_RS232_INPUT (6 * SERIAL_REG_OFS)
#define SERIAL_SCRATCH_PAD (7 * SERIAL_REG_OFS)
#define SERIAL_DIVISOR_LSB (0 * SERIAL_REG_OFS)
#define SERIAL_DIVISOR_MSB (1 * SERIAL_REG_OFS)
/*
* Functions to READ and WRITE to serial port 0
*/
#define SERIAL_READ(ofs) (*((volatile unsigned char*) \
(TITAN_SERIAL_BASE + ofs)))
#define SERIAL_WRITE(ofs, val) ((*((volatile unsigned char*) \
(TITAN_SERIAL_BASE + ofs))) = val)
/*
* Functions to READ and WRITE to serial port 1
*/
#define SERIAL_READ_1(ofs) (*((volatile unsigned char*) \
(TITAN_SERIAL_BASE_1 + ofs)))
#define SERIAL_WRITE_1(ofs, val) ((*((volatile unsigned char*) \
(TITAN_SERIAL_BASE_1 + ofs))) = val)
/*
* Second serial port initialization
*/
void init_second_port(void)
{
/* Disable Interrupts */
SERIAL_WRITE_1(SERIAL_LINE_CONTROL, 0x0);
SERIAL_WRITE_1(SERIAL_INTR_ENABLE, 0x0);
{
unsigned int divisor;
SERIAL_WRITE_1(SERIAL_LINE_CONTROL, 0x80);
divisor = TITAN_SERIAL_BASE_BAUD / YOSEMITE_BAUD_115200;
SERIAL_WRITE_1(SERIAL_DIVISOR_LSB, divisor & 0xff);
SERIAL_WRITE_1(SERIAL_DIVISOR_MSB,
(divisor & 0xff00) >> 8);
SERIAL_WRITE_1(SERIAL_LINE_CONTROL, 0x0);
}
SERIAL_WRITE_1(SERIAL_DATA_FORMAT, YOSEMITE_DATA_8BIT |
YOSEMITE_PARITY_NONE | YOSEMITE_STOP_1BIT);
/* Enable Interrupts */
SERIAL_WRITE_1(SERIAL_INTR_ENABLE, 0xf);
}
/* Initialize the serial port for KGDB debugging */
void debugInit(unsigned int baud, unsigned char data, unsigned char parity,
unsigned char stop)
{
/* Disable Interrupts */
SERIAL_WRITE(SERIAL_LINE_CONTROL, 0x0);
SERIAL_WRITE(SERIAL_INTR_ENABLE, 0x0);
{
unsigned int divisor;
SERIAL_WRITE(SERIAL_LINE_CONTROL, 0x80);
divisor = TITAN_SERIAL_BASE_BAUD / baud;
SERIAL_WRITE(SERIAL_DIVISOR_LSB, divisor & 0xff);
SERIAL_WRITE(SERIAL_DIVISOR_MSB, (divisor & 0xff00) >> 8);
SERIAL_WRITE(SERIAL_LINE_CONTROL, 0x0);
}
SERIAL_WRITE(SERIAL_DATA_FORMAT, data | parity | stop);
}
static int remoteDebugInitialized = 0;
unsigned char getDebugChar(void)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(YOSEMITE_BAUD_115200,
YOSEMITE_DATA_8BIT,
YOSEMITE_PARITY_NONE, YOSEMITE_STOP_1BIT);
}
while ((SERIAL_READ(SERIAL_LINE_STATUS) & 0x1) == 0);
return SERIAL_READ(SERIAL_RCV_BUFFER);
}
int putDebugChar(unsigned char byte)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(YOSEMITE_BAUD_115200,
YOSEMITE_DATA_8BIT,
YOSEMITE_PARITY_NONE, YOSEMITE_STOP_1BIT);
}
while ((SERIAL_READ(SERIAL_LINE_STATUS) & 0x20) == 0);
SERIAL_WRITE(SERIAL_SEND_BUFFER, byte);
return 1;
}

9
arch/mips/pmc-sierra/yosemite/irq.c
View File

@@ -141,10 +141,6 @@ asmlinkage void plat_irq_dispatch(void)
}
}
#ifdef CONFIG_KGDB
extern void init_second_port(void);
#endif
/*
* Initialize the next level interrupt handler
*/
@@ -156,11 +152,6 @@ void __init arch_init_irq(void)
rm7k_cpu_irq_init();
rm9k_cpu_irq_init();
#ifdef CONFIG_KGDB
/* At this point, initialize the second serial port */
init_second_port();
#endif
#ifdef CONFIG_GDB_CONSOLE
register_gdb_console();
#endif