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m68k: generalize io memory region setup for ColdFire ACR registers

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The ACR registers of the ColdFire define at a macro level what regions
of the addresses space should have caching or other attribute types applied.

Currently for the MMU enabled setups we map the interal IO peripheral addres
space as uncachable based on the define for the MBAR address (CONFIG_MBAR).
Not all ColdFire SoC use a programmable MBAR register address. Some parts
have fixed addressing for their internal peripheral registers.

Generalize the way we get the internal peripheral base address so all types
can be accomodated in the ACR definitions. Each ColdFire SoC type now sets
its IO memory base and size definitions (which may be based on MBAR) which
are then used in the ACR definitions.

Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
This commit is contained in:
Greg Ungerer
2016-08-26 15:59:30 +10:00
parent f71160655d
commit 8cf4a973b4
3 changed files with 5 additions and 1 deletions
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2
arch/m68k/include/asm/m54xxacr.h
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@@ -94,7 +94,7 @@
* register region as non-cacheable. And then we map all our RAM as
* cacheable and supervisor access only.
*/
#define ACR0_MODE (ACR_BA(CONFIG_MBAR)+ACR_ADMSK(0x1000000)+ \
#define ACR0_MODE (ACR_BA(IOMEMBASE)+ACR_ADMSK(IOMEMSIZE)+ \
ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP)
#if defined(CONFIG_CACHE_COPYBACK)
#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \