Merge branch 'mips-next-3.9' of git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next
This commit is contained in:
Ralf Baechle
@@ -98,6 +98,9 @@
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#ifndef cpu_has_rixi
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#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
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#endif
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#ifndef cpu_has_mmips
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#define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
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#endif
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#ifndef cpu_has_vtag_icache
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#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
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#endif
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@@ -273,4 +276,8 @@
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#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
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#endif
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#ifndef cpu_has_vz
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#define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ)
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#endif
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#endif /* __ASM_CPU_FEATURES_H */
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@@ -96,6 +96,7 @@
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#define PRID_IMP_1004K 0x9900
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#define PRID_IMP_1074K 0x9a00
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#define PRID_IMP_M14KC 0x9c00
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#define PRID_IMP_M14KEC 0x9e00
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/*
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* These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
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@@ -264,6 +265,7 @@ enum cpu_type_enum {
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CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
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CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
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CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
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CPU_M14KEC,
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/*
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* MIPS64 class processors
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@@ -322,6 +324,7 @@ enum cpu_type_enum {
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#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */
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#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */
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#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */
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#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */
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/*
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* CPU ASE encodings
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@@ -333,6 +336,6 @@ enum cpu_type_enum {
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#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
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#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
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#define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */
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#define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */
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#endif /* _ASM_CPU_H */
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@@ -359,6 +359,7 @@ struct gic_shared_intr_map {
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/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
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#define GIC_PIN_TO_VEC_OFFSET (1)
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extern int gic_present;
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extern unsigned long _gic_base;
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extern unsigned int gic_irq_base;
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extern unsigned int gic_irq_flags[];
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@@ -141,7 +141,7 @@ do { \
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#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
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defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
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defined(CONFIG_CPU_R5500)
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defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR)
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/*
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* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
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@@ -17,4 +17,10 @@ extern void mips_cpu_irq_init(void);
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extern void rm7k_cpu_irq_init(void);
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extern void rm9k_cpu_irq_init(void);
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#ifdef CONFIG_IRQ_DOMAIN
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struct device_node;
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extern int mips_cpu_intc_init(struct device_node *of_node,
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struct device_node *parent);
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#endif
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#endif /* _ASM_IRQ_CPU_H */
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@@ -41,11 +41,37 @@
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#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
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#define AR71XX_RESET_SIZE 0x100
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#define AR71XX_PCI_MEM_BASE 0x10000000
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#define AR71XX_PCI_MEM_SIZE 0x07000000
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#define AR71XX_PCI_WIN0_OFFS 0x10000000
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#define AR71XX_PCI_WIN1_OFFS 0x11000000
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#define AR71XX_PCI_WIN2_OFFS 0x12000000
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#define AR71XX_PCI_WIN3_OFFS 0x13000000
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#define AR71XX_PCI_WIN4_OFFS 0x14000000
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#define AR71XX_PCI_WIN5_OFFS 0x15000000
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#define AR71XX_PCI_WIN6_OFFS 0x16000000
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#define AR71XX_PCI_WIN7_OFFS 0x07000000
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#define AR71XX_PCI_CFG_BASE \
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(AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
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#define AR71XX_PCI_CFG_SIZE 0x100
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#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
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#define AR7240_USB_CTRL_SIZE 0x100
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#define AR7240_OHCI_BASE 0x1b000000
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#define AR7240_OHCI_SIZE 0x1000
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#define AR724X_PCI_MEM_BASE 0x10000000
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#define AR724X_PCI_MEM_SIZE 0x04000000
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#define AR724X_PCI_CFG_BASE 0x14000000
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#define AR724X_PCI_CFG_SIZE 0x1000
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#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000)
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#define AR724X_PCI_CRP_SIZE 0x1000
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#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
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#define AR724X_PCI_CTRL_SIZE 0x100
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#define AR724X_EHCI_BASE 0x1b000000
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#define AR724X_EHCI_SIZE 0x1000
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@@ -68,6 +94,25 @@
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#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
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#define AR934X_SRIF_SIZE 0x1000
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#define QCA955X_PCI_MEM_BASE0 0x10000000
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#define QCA955X_PCI_MEM_BASE1 0x12000000
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#define QCA955X_PCI_MEM_SIZE 0x02000000
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#define QCA955X_PCI_CFG_BASE0 0x14000000
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#define QCA955X_PCI_CFG_BASE1 0x16000000
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#define QCA955X_PCI_CFG_SIZE 0x1000
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#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
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#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
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#define QCA955X_PCI_CRP_SIZE 0x1000
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#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
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#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
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#define QCA955X_PCI_CTRL_SIZE 0x100
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#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
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#define QCA955X_WMAC_SIZE 0x20000
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#define QCA955X_EHCI0_BASE 0x1b000000
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#define QCA955X_EHCI1_BASE 0x1b400000
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#define QCA955X_EHCI_SIZE 0x1000
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/*
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* DDR_CTRL block
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*/
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@@ -199,6 +244,41 @@
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
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#define QCA955X_PLL_CPU_CONFIG_REG 0x00
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#define QCA955X_PLL_DDR_CONFIG_REG 0x04
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#define QCA955X_PLL_CLK_CTRL_REG 0x08
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#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
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#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
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#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6
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#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f
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#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
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#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
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#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
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#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
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#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
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#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
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#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10
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#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f
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#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
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#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
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#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
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#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
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#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
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#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
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#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
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#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
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#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
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#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
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#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
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#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
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#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
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#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
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#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
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#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
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/*
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* USB_CONFIG block
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*/
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@@ -238,6 +318,10 @@
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#define AR934X_RESET_REG_BOOTSTRAP 0xb0
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#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
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#define QCA955X_RESET_REG_RESET_MODULE 0x1c
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#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
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#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
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#define MISC_INT_ETHSW BIT(12)
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#define MISC_INT_TIMER4 BIT(10)
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#define MISC_INT_TIMER3 BIT(9)
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@@ -315,6 +399,8 @@
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#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
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#define AR934X_BOOTSTRAP_DDR1 BIT(0)
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#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
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#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
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#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
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#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
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@@ -333,6 +419,37 @@
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AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
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AR934X_PCIE_WMAC_INT_PCIE_RC3)
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#define QCA955X_EXT_INT_WMAC_MISC BIT(0)
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#define QCA955X_EXT_INT_WMAC_TX BIT(1)
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#define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
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#define QCA955X_EXT_INT_WMAC_RXHP BIT(3)
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#define QCA955X_EXT_INT_PCIE_RC1 BIT(4)
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#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5)
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#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6)
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#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7)
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#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8)
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#define QCA955X_EXT_INT_PCIE_RC2 BIT(12)
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#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13)
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#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14)
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#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15)
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#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16)
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#define QCA955X_EXT_INT_USB1 BIT(24)
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#define QCA955X_EXT_INT_USB2 BIT(28)
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#define QCA955X_EXT_INT_WMAC_ALL \
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(QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
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QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
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#define QCA955X_EXT_INT_PCIE_RC1_ALL \
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(QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
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QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
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QCA955X_EXT_INT_PCIE_RC1_INT3)
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#define QCA955X_EXT_INT_PCIE_RC2_ALL \
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(QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
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QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
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QCA955X_EXT_INT_PCIE_RC2_INT3)
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#define REV_ID_MAJOR_MASK 0xfff0
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#define REV_ID_MAJOR_AR71XX 0x00a0
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#define REV_ID_MAJOR_AR913X 0x00b0
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@@ -344,6 +461,8 @@
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#define REV_ID_MAJOR_AR9341 0x0120
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#define REV_ID_MAJOR_AR9342 0x1120
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#define REV_ID_MAJOR_AR9344 0x2120
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#define REV_ID_MAJOR_QCA9556 0x0130
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#define REV_ID_MAJOR_QCA9558 0x1130
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#define AR71XX_REV_ID_MINOR_MASK 0x3
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#define AR71XX_REV_ID_MINOR_AR7130 0x0
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@@ -364,6 +483,8 @@
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#define AR934X_REV_ID_REVISION_MASK 0xf
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#define QCA955X_REV_ID_REVISION_MASK 0xf
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/*
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* SPI block
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*/
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@@ -401,12 +522,15 @@
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#define AR71XX_GPIO_REG_INT_ENABLE 0x24
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#define AR71XX_GPIO_REG_FUNC 0x28
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#define AR934X_GPIO_REG_FUNC 0x6c
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#define AR71XX_GPIO_COUNT 16
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#define AR7240_GPIO_COUNT 18
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#define AR7241_GPIO_COUNT 20
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#define AR913X_GPIO_COUNT 22
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#define AR933X_GPIO_COUNT 30
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#define AR934X_GPIO_COUNT 23
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#define QCA955X_GPIO_COUNT 24
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/*
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* SRIF block
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@@ -32,6 +32,8 @@ enum ath79_soc_type {
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ATH79_SOC_AR9341,
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ATH79_SOC_AR9342,
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ATH79_SOC_AR9344,
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ATH79_SOC_QCA9556,
|
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ATH79_SOC_QCA9558,
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};
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extern enum ath79_soc_type ath79_soc;
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@@ -98,6 +100,21 @@ static inline int soc_is_ar934x(void)
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return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
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}
|
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|
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static inline int soc_is_qca9556(void)
|
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{
|
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return ath79_soc == ATH79_SOC_QCA9556;
|
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}
|
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|
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static inline int soc_is_qca9558(void)
|
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{
|
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return ath79_soc == ATH79_SOC_QCA9558;
|
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}
|
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|
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static inline int soc_is_qca955x(void)
|
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{
|
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return soc_is_qca9556() || soc_is_qca9558();
|
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}
|
||||
|
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extern void __iomem *ath79_ddr_base;
|
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extern void __iomem *ath79_pll_base;
|
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extern void __iomem *ath79_reset_base;
|
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|
||||
@@ -10,10 +10,13 @@
|
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#define __ASM_MACH_ATH79_IRQ_H
|
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|
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#define MIPS_CPU_IRQ_BASE 0
|
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#define NR_IRQS 48
|
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#define NR_IRQS 51
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#define ATH79_CPU_IRQ(_x) (MIPS_CPU_IRQ_BASE + (_x))
|
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|
||||
#define ATH79_MISC_IRQ_BASE 8
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#define ATH79_MISC_IRQ_COUNT 32
|
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#define ATH79_MISC_IRQ(_x) (ATH79_MISC_IRQ_BASE + (_x))
|
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|
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#define ATH79_PCI_IRQ_BASE (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT)
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#define ATH79_PCI_IRQ_COUNT 6
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@@ -23,25 +26,9 @@
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#define ATH79_IP2_IRQ_COUNT 2
|
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#define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x))
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#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
|
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#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
|
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#define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4)
|
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#define ATH79_CPU_IRQ_GE1 (MIPS_CPU_IRQ_BASE + 5)
|
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#define ATH79_CPU_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6)
|
||||
#define ATH79_CPU_IRQ_TIMER (MIPS_CPU_IRQ_BASE + 7)
|
||||
|
||||
#define ATH79_MISC_IRQ_TIMER (ATH79_MISC_IRQ_BASE + 0)
|
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#define ATH79_MISC_IRQ_ERROR (ATH79_MISC_IRQ_BASE + 1)
|
||||
#define ATH79_MISC_IRQ_GPIO (ATH79_MISC_IRQ_BASE + 2)
|
||||
#define ATH79_MISC_IRQ_UART (ATH79_MISC_IRQ_BASE + 3)
|
||||
#define ATH79_MISC_IRQ_WDOG (ATH79_MISC_IRQ_BASE + 4)
|
||||
#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5)
|
||||
#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6)
|
||||
#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7)
|
||||
#define ATH79_MISC_IRQ_TIMER2 (ATH79_MISC_IRQ_BASE + 8)
|
||||
#define ATH79_MISC_IRQ_TIMER3 (ATH79_MISC_IRQ_BASE + 9)
|
||||
#define ATH79_MISC_IRQ_TIMER4 (ATH79_MISC_IRQ_BASE + 10)
|
||||
#define ATH79_MISC_IRQ_ETHSW (ATH79_MISC_IRQ_BASE + 12)
|
||||
#define ATH79_IP3_IRQ_BASE (ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT)
|
||||
#define ATH79_IP3_IRQ_COUNT 3
|
||||
#define ATH79_IP3_IRQ(_x) (ATH79_IP3_IRQ_BASE + (_x))
|
||||
|
||||
#include_next <irq.h>
|
||||
|
||||
|
||||
@@ -1,28 +0,0 @@
|
||||
/*
|
||||
* Atheros AR71XX/AR724X PCI support
|
||||
*
|
||||
* Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
|
||||
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_MACH_ATH79_PCI_H
|
||||
#define __ASM_MACH_ATH79_PCI_H
|
||||
|
||||
#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX)
|
||||
int ar71xx_pcibios_init(void);
|
||||
#else
|
||||
static inline int ar71xx_pcibios_init(void) { return 0; }
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI_AR724X)
|
||||
int ar724x_pcibios_init(int irq);
|
||||
#else
|
||||
static inline int ar724x_pcibios_init(int irq) { return 0; }
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_MACH_ATH79_PCI_H */
|
||||
@@ -8,8 +8,8 @@
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __NVRAM_H
|
||||
#define __NVRAM_H
|
||||
#ifndef __BCM47XX_NVRAM_H
|
||||
#define __BCM47XX_NVRAM_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
@@ -32,12 +32,9 @@ struct nvram_header {
|
||||
#define NVRAM_MAX_VALUE_LEN 255
|
||||
#define NVRAM_MAX_PARAM_LEN 64
|
||||
|
||||
#define NVRAM_ERR_INV_PARAM -8
|
||||
#define NVRAM_ERR_ENVNOTFOUND -9
|
||||
extern int bcm47xx_nvram_getenv(char *name, char *val, size_t val_len);
|
||||
|
||||
extern int nvram_getenv(char *name, char *val, size_t val_len);
|
||||
|
||||
static inline void nvram_parse_macaddr(char *buf, u8 macaddr[6])
|
||||
static inline void bcm47xx_nvram_parse_macaddr(char *buf, u8 macaddr[6])
|
||||
{
|
||||
if (strchr(buf, ':'))
|
||||
sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0],
|
||||
@@ -51,4 +48,4 @@ static inline void nvram_parse_macaddr(char *buf, u8 macaddr[6])
|
||||
printk(KERN_WARNING "Can not parse mac address: %s\n", buf);
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif /* __BCM47XX_NVRAM_H */
|
||||
@@ -34,6 +34,7 @@ extern spinlock_t ebu_lock;
|
||||
extern void ltq_disable_irq(struct irq_data *data);
|
||||
extern void ltq_mask_and_ack_irq(struct irq_data *data);
|
||||
extern void ltq_enable_irq(struct irq_data *data);
|
||||
extern int ltq_eiu_get_irq(int exin);
|
||||
|
||||
/* clock handling */
|
||||
extern int clk_activate(struct clk *clk);
|
||||
@@ -41,6 +42,7 @@ extern void clk_deactivate(struct clk *clk);
|
||||
extern struct clk *clk_get_cpu(void);
|
||||
extern struct clk *clk_get_fpi(void);
|
||||
extern struct clk *clk_get_io(void);
|
||||
extern struct clk *clk_get_ppe(void);
|
||||
|
||||
/* find out what bootsource we have */
|
||||
extern unsigned char ltq_boot_select(void);
|
||||
|
||||
39
arch/mips/include/asm/mach-ralink/ralink_regs.h
Normal file
39
arch/mips/include/asm/mach-ralink/ralink_regs.h
Normal file
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Ralink SoC register definitions
|
||||
*
|
||||
* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _RALINK_REGS_H_
|
||||
#define _RALINK_REGS_H_
|
||||
|
||||
extern __iomem void *rt_sysc_membase;
|
||||
extern __iomem void *rt_memc_membase;
|
||||
|
||||
static inline void rt_sysc_w32(u32 val, unsigned reg)
|
||||
{
|
||||
__raw_writel(val, rt_sysc_membase + reg);
|
||||
}
|
||||
|
||||
static inline u32 rt_sysc_r32(unsigned reg)
|
||||
{
|
||||
return __raw_readl(rt_sysc_membase + reg);
|
||||
}
|
||||
|
||||
static inline void rt_memc_w32(u32 val, unsigned reg)
|
||||
{
|
||||
__raw_writel(val, rt_memc_membase + reg);
|
||||
}
|
||||
|
||||
static inline u32 rt_memc_r32(unsigned reg)
|
||||
{
|
||||
return __raw_readl(rt_memc_membase + reg);
|
||||
}
|
||||
|
||||
#endif /* _RALINK_REGS_H_ */
|
||||
139
arch/mips/include/asm/mach-ralink/rt305x.h
Normal file
139
arch/mips/include/asm/mach-ralink/rt305x.h
Normal file
@@ -0,0 +1,139 @@
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*
|
||||
* Parts of this file are based on Ralink's 2.6.21 BSP
|
||||
*
|
||||
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
|
||||
#ifndef _RT305X_REGS_H_
|
||||
#define _RT305X_REGS_H_
|
||||
|
||||
enum rt305x_soc_type {
|
||||
RT305X_SOC_UNKNOWN = 0,
|
||||
RT305X_SOC_RT3050,
|
||||
RT305X_SOC_RT3052,
|
||||
RT305X_SOC_RT3350,
|
||||
RT305X_SOC_RT3352,
|
||||
RT305X_SOC_RT5350,
|
||||
};
|
||||
|
||||
extern enum rt305x_soc_type rt305x_soc;
|
||||
|
||||
static inline int soc_is_rt3050(void)
|
||||
{
|
||||
return rt305x_soc == RT305X_SOC_RT3050;
|
||||
}
|
||||
|
||||
static inline int soc_is_rt3052(void)
|
||||
{
|
||||
return rt305x_soc == RT305X_SOC_RT3052;
|
||||
}
|
||||
|
||||
static inline int soc_is_rt305x(void)
|
||||
{
|
||||
return soc_is_rt3050() || soc_is_rt3052();
|
||||
}
|
||||
|
||||
static inline int soc_is_rt3350(void)
|
||||
{
|
||||
return rt305x_soc == RT305X_SOC_RT3350;
|
||||
}
|
||||
|
||||
static inline int soc_is_rt3352(void)
|
||||
{
|
||||
return rt305x_soc == RT305X_SOC_RT3352;
|
||||
}
|
||||
|
||||
static inline int soc_is_rt5350(void)
|
||||
{
|
||||
return rt305x_soc == RT305X_SOC_RT5350;
|
||||
}
|
||||
|
||||
#define RT305X_SYSC_BASE 0x10000000
|
||||
|
||||
#define SYSC_REG_CHIP_NAME0 0x00
|
||||
#define SYSC_REG_CHIP_NAME1 0x04
|
||||
#define SYSC_REG_CHIP_ID 0x0c
|
||||
#define SYSC_REG_SYSTEM_CONFIG 0x10
|
||||
|
||||
#define RT3052_CHIP_NAME0 0x30335452
|
||||
#define RT3052_CHIP_NAME1 0x20203235
|
||||
|
||||
#define RT3350_CHIP_NAME0 0x33335452
|
||||
#define RT3350_CHIP_NAME1 0x20203035
|
||||
|
||||
#define RT3352_CHIP_NAME0 0x33335452
|
||||
#define RT3352_CHIP_NAME1 0x20203235
|
||||
|
||||
#define RT5350_CHIP_NAME0 0x33355452
|
||||
#define RT5350_CHIP_NAME1 0x20203035
|
||||
|
||||
#define CHIP_ID_ID_MASK 0xff
|
||||
#define CHIP_ID_ID_SHIFT 8
|
||||
#define CHIP_ID_REV_MASK 0xff
|
||||
|
||||
#define RT305X_SYSCFG_CPUCLK_SHIFT 18
|
||||
#define RT305X_SYSCFG_CPUCLK_MASK 0x1
|
||||
#define RT305X_SYSCFG_CPUCLK_LOW 0x0
|
||||
#define RT305X_SYSCFG_CPUCLK_HIGH 0x1
|
||||
|
||||
#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2
|
||||
#define RT305X_SYSCFG_CPUCLK_MASK 0x1
|
||||
#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 0x1
|
||||
|
||||
#define RT3352_SYSCFG0_CPUCLK_SHIFT 8
|
||||
#define RT3352_SYSCFG0_CPUCLK_MASK 0x1
|
||||
#define RT3352_SYSCFG0_CPUCLK_LOW 0x0
|
||||
#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1
|
||||
|
||||
#define RT5350_SYSCFG0_CPUCLK_SHIFT 8
|
||||
#define RT5350_SYSCFG0_CPUCLK_MASK 0x3
|
||||
#define RT5350_SYSCFG0_CPUCLK_360 0x0
|
||||
#define RT5350_SYSCFG0_CPUCLK_320 0x2
|
||||
#define RT5350_SYSCFG0_CPUCLK_300 0x3
|
||||
|
||||
/* multi function gpio pins */
|
||||
#define RT305X_GPIO_I2C_SD 1
|
||||
#define RT305X_GPIO_I2C_SCLK 2
|
||||
#define RT305X_GPIO_SPI_EN 3
|
||||
#define RT305X_GPIO_SPI_CLK 4
|
||||
/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */
|
||||
#define RT305X_GPIO_7 7
|
||||
#define RT305X_GPIO_10 10
|
||||
#define RT305X_GPIO_14 14
|
||||
#define RT305X_GPIO_UART1_TXD 15
|
||||
#define RT305X_GPIO_UART1_RXD 16
|
||||
#define RT305X_GPIO_JTAG_TDO 17
|
||||
#define RT305X_GPIO_JTAG_TDI 18
|
||||
#define RT305X_GPIO_MDIO_MDC 22
|
||||
#define RT305X_GPIO_MDIO_MDIO 23
|
||||
#define RT305X_GPIO_SDRAM_MD16 24
|
||||
#define RT305X_GPIO_SDRAM_MD31 39
|
||||
#define RT305X_GPIO_GE0_TXD0 40
|
||||
#define RT305X_GPIO_GE0_RXCLK 51
|
||||
|
||||
#define RT305X_GPIO_MODE_I2C BIT(0)
|
||||
#define RT305X_GPIO_MODE_SPI BIT(1)
|
||||
#define RT305X_GPIO_MODE_UART0_SHIFT 2
|
||||
#define RT305X_GPIO_MODE_UART0_MASK 0x7
|
||||
#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
|
||||
#define RT305X_GPIO_MODE_UARTF 0x0
|
||||
#define RT305X_GPIO_MODE_PCM_UARTF 0x1
|
||||
#define RT305X_GPIO_MODE_PCM_I2S 0x2
|
||||
#define RT305X_GPIO_MODE_I2S_UARTF 0x3
|
||||
#define RT305X_GPIO_MODE_PCM_GPIO 0x4
|
||||
#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
|
||||
#define RT305X_GPIO_MODE_GPIO_I2S 0x6
|
||||
#define RT305X_GPIO_MODE_GPIO 0x7
|
||||
#define RT305X_GPIO_MODE_UART1 BIT(5)
|
||||
#define RT305X_GPIO_MODE_JTAG BIT(6)
|
||||
#define RT305X_GPIO_MODE_MDIO BIT(7)
|
||||
#define RT305X_GPIO_MODE_SDRAM BIT(8)
|
||||
#define RT305X_GPIO_MODE_RGMII BIT(9)
|
||||
|
||||
#endif
|
||||
25
arch/mips/include/asm/mach-ralink/war.h
Normal file
25
arch/mips/include/asm/mach-ralink/war.h
Normal file
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
|
||||
*/
|
||||
#ifndef __ASM_MACH_RALINK_WAR_H
|
||||
#define __ASM_MACH_RALINK_WAR_H
|
||||
|
||||
#define R4600_V1_INDEX_ICACHEOP_WAR 0
|
||||
#define R4600_V1_HIT_CACHEOP_WAR 0
|
||||
#define R4600_V2_HIT_CACHEOP_WAR 0
|
||||
#define R5432_CP0_INTERRUPT_WAR 0
|
||||
#define BCM1250_M3_WAR 0
|
||||
#define SIBYTE_1956_WAR 0
|
||||
#define MIPS4K_ICACHE_REFILL_WAR 0
|
||||
#define MIPS_CACHE_SYNC_WAR 0
|
||||
#define TX49XX_ICACHE_INDEX_INV_WAR 0
|
||||
#define RM9000_CDEX_SMP_WAR 0
|
||||
#define ICACHE_REFILLS_WORKAROUND_WAR 0
|
||||
#define R10000_LLSC_WAR 0
|
||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
||||
|
||||
#endif /* __ASM_MACH_RALINK_WAR_H */
|
||||
@@ -1,21 +1,14 @@
|
||||
/*
|
||||
* Carsten Langgaard, carstenl@mips.com
|
||||
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can distribute it and/or modify it
|
||||
* under the terms of the GNU General Public License (Version 2) as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
||||
*
|
||||
* Defines of the MIPS boards specific address-MAP, registers, etc.
|
||||
*
|
||||
* Copyright (C) 2000,2012 MIPS Technologies, Inc.
|
||||
* All rights reserved.
|
||||
* Authors: Carsten Langgaard <carstenl@mips.com>
|
||||
* Steven J. Hill <sjhill@mips.com>
|
||||
*/
|
||||
#ifndef __ASM_MIPS_BOARDS_GENERIC_H
|
||||
#define __ASM_MIPS_BOARDS_GENERIC_H
|
||||
@@ -30,13 +23,6 @@
|
||||
#define ASCII_DISPLAY_WORD_BASE 0x1f000410
|
||||
#define ASCII_DISPLAY_POS_BASE 0x1f000418
|
||||
|
||||
|
||||
/*
|
||||
* Yamon Prom print address.
|
||||
*/
|
||||
#define YAMON_PROM_PRINT_ADDR 0x1fc00504
|
||||
|
||||
|
||||
/*
|
||||
* Reset register.
|
||||
*/
|
||||
|
||||
@@ -595,6 +595,8 @@
|
||||
#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
|
||||
#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
|
||||
#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
|
||||
#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
|
||||
#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
|
||||
|
||||
#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
|
||||
#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
|
||||
@@ -1158,6 +1160,136 @@ do { \
|
||||
__res; \
|
||||
})
|
||||
|
||||
#ifdef HAVE_AS_DSP
|
||||
#define rddsp(mask) \
|
||||
({ \
|
||||
unsigned int __dspctl; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" rddsp %0, %x1 \n" \
|
||||
: "=r" (__dspctl) \
|
||||
: "i" (mask)); \
|
||||
__dspctl; \
|
||||
})
|
||||
|
||||
#define wrdsp(val, mask) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" wrdsp %0, %x1 \n" \
|
||||
: \
|
||||
: "r" (val), "i" (mask)); \
|
||||
} while (0)
|
||||
|
||||
#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
|
||||
#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
|
||||
#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
|
||||
#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
|
||||
|
||||
#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
|
||||
#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
|
||||
#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
|
||||
#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
|
||||
|
||||
#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
|
||||
#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
|
||||
#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
|
||||
#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
|
||||
|
||||
#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
|
||||
#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
|
||||
#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
|
||||
#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
|
||||
|
||||
#else
|
||||
|
||||
#ifdef CONFIG_CPU_MICROMIPS
|
||||
#define rddsp(mask) \
|
||||
({ \
|
||||
unsigned int __res; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # rddsp $1, %x1 \n" \
|
||||
" .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \
|
||||
" .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__res) \
|
||||
: "i" (mask)); \
|
||||
__res; \
|
||||
})
|
||||
|
||||
#define wrdsp(val, mask) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # wrdsp $1, %x1 \n" \
|
||||
" .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \
|
||||
" .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (val), "i" (mask)); \
|
||||
} while (0)
|
||||
|
||||
#define _umips_dsp_mfxxx(ins) \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" .hword 0x0001 \n" \
|
||||
" .hword %x1 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg) \
|
||||
: "i" (ins)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define _umips_dsp_mtxxx(val, ins) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" .hword 0x0001 \n" \
|
||||
" .hword %x1 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (val), "i" (ins)); \
|
||||
} while (0)
|
||||
|
||||
#define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
|
||||
#define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
|
||||
|
||||
#define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
|
||||
#define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
|
||||
|
||||
#define mflo0() _umips_dsp_mflo(0)
|
||||
#define mflo1() _umips_dsp_mflo(1)
|
||||
#define mflo2() _umips_dsp_mflo(2)
|
||||
#define mflo3() _umips_dsp_mflo(3)
|
||||
|
||||
#define mfhi0() _umips_dsp_mfhi(0)
|
||||
#define mfhi1() _umips_dsp_mfhi(1)
|
||||
#define mfhi2() _umips_dsp_mfhi(2)
|
||||
#define mfhi3() _umips_dsp_mfhi(3)
|
||||
|
||||
#define mtlo0(x) _umips_dsp_mtlo(x, 0)
|
||||
#define mtlo1(x) _umips_dsp_mtlo(x, 1)
|
||||
#define mtlo2(x) _umips_dsp_mtlo(x, 2)
|
||||
#define mtlo3(x) _umips_dsp_mtlo(x, 3)
|
||||
|
||||
#define mthi0(x) _umips_dsp_mthi(x, 0)
|
||||
#define mthi1(x) _umips_dsp_mthi(x, 1)
|
||||
#define mthi2(x) _umips_dsp_mthi(x, 2)
|
||||
#define mthi3(x) _umips_dsp_mthi(x, 3)
|
||||
|
||||
#else /* !CONFIG_CPU_MICROMIPS */
|
||||
#define rddsp(mask) \
|
||||
({ \
|
||||
unsigned int __res; \
|
||||
@@ -1183,257 +1315,64 @@ do { \
|
||||
" # wrdsp $1, %x1 \n" \
|
||||
" .word 0x7c2004f8 | (%x1 << 11) \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: \
|
||||
: "r" (val), "i" (mask)); \
|
||||
} while (0)
|
||||
|
||||
#if 0 /* Need DSP ASE capable assembler ... */
|
||||
#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
|
||||
#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
|
||||
#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
|
||||
#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
|
||||
|
||||
#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
|
||||
#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
|
||||
#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
|
||||
#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
|
||||
|
||||
#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
|
||||
#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
|
||||
#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
|
||||
#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
|
||||
|
||||
#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
|
||||
#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
|
||||
#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
|
||||
#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
|
||||
|
||||
#else
|
||||
|
||||
#define mfhi0() \
|
||||
#define _dsp_mfxxx(ins) \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mfhi %0, $ac0 \n" \
|
||||
" .word 0x00000810 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" .word (0x00000810 | %1) \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg) \
|
||||
: "i" (ins)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mfhi1() \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mfhi %0, $ac1 \n" \
|
||||
" .word 0x00200810 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mfhi2() \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mfhi %0, $ac2 \n" \
|
||||
" .word 0x00400810 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mfhi3() \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mfhi %0, $ac3 \n" \
|
||||
" .word 0x00600810 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mflo0() \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mflo %0, $ac0 \n" \
|
||||
" .word 0x00000812 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mflo1() \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mflo %0, $ac1 \n" \
|
||||
" .word 0x00200812 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mflo2() \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mflo %0, $ac2 \n" \
|
||||
" .word 0x00400812 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mflo3() \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mflo %0, $ac3 \n" \
|
||||
" .word 0x00600812 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mthi0(x) \
|
||||
#define _dsp_mtxxx(val, ins) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mthi $1, $ac0 \n" \
|
||||
" .word 0x00200011 \n" \
|
||||
" .word (0x00200011 | %1) \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
: "r" (val), "i" (ins)); \
|
||||
} while (0)
|
||||
|
||||
#define mthi1(x) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mthi $1, $ac1 \n" \
|
||||
" .word 0x00200811 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
} while (0)
|
||||
#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
|
||||
#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
|
||||
|
||||
#define mthi2(x) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mthi $1, $ac2 \n" \
|
||||
" .word 0x00201011 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
} while (0)
|
||||
#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
|
||||
#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
|
||||
|
||||
#define mthi3(x) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mthi $1, $ac3 \n" \
|
||||
" .word 0x00201811 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
} while (0)
|
||||
#define mflo0() _dsp_mflo(0)
|
||||
#define mflo1() _dsp_mflo(1)
|
||||
#define mflo2() _dsp_mflo(2)
|
||||
#define mflo3() _dsp_mflo(3)
|
||||
|
||||
#define mtlo0(x) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mtlo $1, $ac0 \n" \
|
||||
" .word 0x00200013 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
} while (0)
|
||||
#define mfhi0() _dsp_mfhi(0)
|
||||
#define mfhi1() _dsp_mfhi(1)
|
||||
#define mfhi2() _dsp_mfhi(2)
|
||||
#define mfhi3() _dsp_mfhi(3)
|
||||
|
||||
#define mtlo1(x) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mtlo $1, $ac1 \n" \
|
||||
" .word 0x00200813 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
} while (0)
|
||||
#define mtlo0(x) _dsp_mtlo(x, 0)
|
||||
#define mtlo1(x) _dsp_mtlo(x, 1)
|
||||
#define mtlo2(x) _dsp_mtlo(x, 2)
|
||||
#define mtlo3(x) _dsp_mtlo(x, 3)
|
||||
|
||||
#define mtlo2(x) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mtlo $1, $ac2 \n" \
|
||||
" .word 0x00201013 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
} while (0)
|
||||
|
||||
#define mtlo3(x) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mtlo $1, $ac3 \n" \
|
||||
" .word 0x00201813 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
} while (0)
|
||||
#define mthi0(x) _dsp_mthi(x, 0)
|
||||
#define mthi1(x) _dsp_mthi(x, 1)
|
||||
#define mthi2(x) _dsp_mthi(x, 2)
|
||||
#define mthi3(x) _dsp_mthi(x, 3)
|
||||
|
||||
#endif /* CONFIG_CPU_MICROMIPS */
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
||||
@@ -68,6 +68,85 @@ do { \
|
||||
__write_64bit_c0_register($9, 7, (val)); \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
* Handling the 64 bit EIMR and EIRR registers in 32-bit mode with
|
||||
* standard functions will be very inefficient. This provides
|
||||
* optimized functions for the normal operations on the registers.
|
||||
*
|
||||
* Call with interrupts disabled.
|
||||
*/
|
||||
static inline void ack_c0_eirr(int irq)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
".set push\n\t"
|
||||
".set mips64\n\t"
|
||||
".set noat\n\t"
|
||||
"li $1, 1\n\t"
|
||||
"dsllv $1, $1, %0\n\t"
|
||||
"dmtc0 $1, $9, 6\n\t"
|
||||
".set pop"
|
||||
: : "r" (irq));
|
||||
}
|
||||
|
||||
static inline void set_c0_eimr(int irq)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
".set push\n\t"
|
||||
".set mips64\n\t"
|
||||
".set noat\n\t"
|
||||
"li $1, 1\n\t"
|
||||
"dsllv %0, $1, %0\n\t"
|
||||
"dmfc0 $1, $9, 7\n\t"
|
||||
"or $1, %0\n\t"
|
||||
"dmtc0 $1, $9, 7\n\t"
|
||||
".set pop"
|
||||
: "+r" (irq));
|
||||
}
|
||||
|
||||
static inline void clear_c0_eimr(int irq)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
".set push\n\t"
|
||||
".set mips64\n\t"
|
||||
".set noat\n\t"
|
||||
"li $1, 1\n\t"
|
||||
"dsllv %0, $1, %0\n\t"
|
||||
"dmfc0 $1, $9, 7\n\t"
|
||||
"or $1, %0\n\t"
|
||||
"xor $1, %0\n\t"
|
||||
"dmtc0 $1, $9, 7\n\t"
|
||||
".set pop"
|
||||
: "+r" (irq));
|
||||
}
|
||||
|
||||
/*
|
||||
* Read c0 eimr and c0 eirr, do AND of the two values, the result is
|
||||
* the interrupts which are raised and are not masked.
|
||||
*/
|
||||
static inline uint64_t read_c0_eirr_and_eimr(void)
|
||||
{
|
||||
uint64_t val;
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
val = read_c0_eimr() & read_c0_eirr();
|
||||
#else
|
||||
__asm__ __volatile__(
|
||||
".set push\n\t"
|
||||
".set mips64\n\t"
|
||||
".set noat\n\t"
|
||||
"dmfc0 %M0, $9, 6\n\t"
|
||||
"dmfc0 %L0, $9, 7\n\t"
|
||||
"and %M0, %L0\n\t"
|
||||
"dsll %L0, %M0, 32\n\t"
|
||||
"dsra %M0, %M0, 32\n\t"
|
||||
"dsra %L0, %L0, 32\n\t"
|
||||
".set pop"
|
||||
: "=r" (val));
|
||||
#endif
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline int hard_smp_processor_id(void)
|
||||
{
|
||||
return __read_32bit_c0_register($15, 1) & 0x3ff;
|
||||
|
||||
@@ -46,6 +46,8 @@
|
||||
#define CPU_BLOCKID_FPU 9
|
||||
#define CPU_BLOCKID_MAP 10
|
||||
|
||||
#define ICU_DEFEATURE 0x100
|
||||
|
||||
#define LSU_DEFEATURE 0x304
|
||||
#define LSU_DEBUG_ADDR 0x305
|
||||
#define LSU_DEBUG_DATA0 0x306
|
||||
|
||||
@@ -261,6 +261,8 @@
|
||||
#define PIC_LOCAL_SCHEDULING 1
|
||||
#define PIC_GLOBAL_SCHEDULING 0
|
||||
|
||||
#define PIC_CLK_HZ 133333333
|
||||
|
||||
#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r)
|
||||
#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
|
||||
#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
|
||||
@@ -315,6 +317,12 @@ nlm_pic_read_timer(uint64_t base, int timer)
|
||||
return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
|
||||
}
|
||||
|
||||
static inline uint32_t
|
||||
nlm_pic_read_timer32(uint64_t base, int timer)
|
||||
{
|
||||
return (uint32_t)nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
|
||||
}
|
||||
|
||||
static inline void
|
||||
nlm_pic_write_timer(uint64_t base, int timer, uint64_t value)
|
||||
{
|
||||
@@ -376,9 +384,9 @@ nlm_pic_ack(uint64_t base, int irt_num)
|
||||
}
|
||||
|
||||
static inline void
|
||||
nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
|
||||
nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en)
|
||||
{
|
||||
nlm_pic_write_irt_direct(base, irt, 0, 0, 0, irq, hwt);
|
||||
nlm_pic_write_irt_direct(base, irt, en, 0, 0, irq, hwt);
|
||||
}
|
||||
|
||||
int nlm_irq_to_irt(int irq);
|
||||
|
||||
@@ -35,10 +35,11 @@
|
||||
#ifndef _ASM_NLM_XLR_PIC_H
|
||||
#define _ASM_NLM_XLR_PIC_H
|
||||
|
||||
#define PIC_CLKS_PER_SEC 66666666ULL
|
||||
#define PIC_CLK_HZ 66666666
|
||||
/* PIC hardware interrupt numbers */
|
||||
#define PIC_IRT_WD_INDEX 0
|
||||
#define PIC_IRT_TIMER_0_INDEX 1
|
||||
#define PIC_IRT_TIMER_INDEX(i) ((i) + PIC_IRT_TIMER_0_INDEX)
|
||||
#define PIC_IRT_TIMER_1_INDEX 2
|
||||
#define PIC_IRT_TIMER_2_INDEX 3
|
||||
#define PIC_IRT_TIMER_3_INDEX 4
|
||||
@@ -99,6 +100,7 @@
|
||||
|
||||
/* PIC Registers */
|
||||
#define PIC_CTRL 0x00
|
||||
#define PIC_CTRL_STE 8 /* timer enable start bit */
|
||||
#define PIC_IPI 0x04
|
||||
#define PIC_INT_ACK 0x06
|
||||
|
||||
@@ -251,12 +253,52 @@ nlm_pic_ack(uint64_t base, int irt)
|
||||
}
|
||||
|
||||
static inline void
|
||||
nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
|
||||
nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en)
|
||||
{
|
||||
nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt));
|
||||
/* local scheduling, invalid, level by default */
|
||||
nlm_write_reg(base, PIC_IRT_1(irt),
|
||||
(1 << 30) | (1 << 6) | irq);
|
||||
(en << 30) | (1 << 6) | irq);
|
||||
}
|
||||
|
||||
static inline uint64_t
|
||||
nlm_pic_read_timer(uint64_t base, int timer)
|
||||
{
|
||||
uint32_t up1, up2, low;
|
||||
|
||||
up1 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer));
|
||||
low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer));
|
||||
up2 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer));
|
||||
|
||||
if (up1 != up2) /* wrapped, get the new low */
|
||||
low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer));
|
||||
return ((uint64_t)up2 << 32) | low;
|
||||
|
||||
}
|
||||
|
||||
static inline uint32_t
|
||||
nlm_pic_read_timer32(uint64_t base, int timer)
|
||||
{
|
||||
return nlm_read_reg(base, PIC_TIMER_COUNT_0(timer));
|
||||
}
|
||||
|
||||
static inline void
|
||||
nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)
|
||||
{
|
||||
uint32_t up, low;
|
||||
uint64_t pic_ctrl = nlm_read_reg(base, PIC_CTRL);
|
||||
int en;
|
||||
|
||||
en = (irq > 0);
|
||||
up = value >> 32;
|
||||
low = value & 0xFFFFFFFF;
|
||||
nlm_write_reg(base, PIC_TIMER_MAXVAL_0(timer), low);
|
||||
nlm_write_reg(base, PIC_TIMER_MAXVAL_1(timer), up);
|
||||
nlm_pic_init_irt(base, PIC_IRT_TIMER_INDEX(timer), irq, cpu, 0);
|
||||
|
||||
/* enable the timer */
|
||||
pic_ctrl |= (1 << (PIC_CTRL_STE + timer));
|
||||
nlm_write_reg(base, PIC_CTRL, pic_ctrl);
|
||||
}
|
||||
#endif
|
||||
#endif /* _ASM_NLM_XLR_PIC_H */
|
||||
|
||||
@@ -144,8 +144,13 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
|
||||
|
||||
extern char * (*pcibios_plat_setup)(char *str);
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
/* this function parses memory ranges from a device node */
|
||||
extern void pci_load_of_ranges(struct pci_controller *hose,
|
||||
struct device_node *node);
|
||||
#else
|
||||
static inline void pci_load_of_ranges(struct pci_controller *hose,
|
||||
struct device_node *node) {}
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_PCI_H */
|
||||
|
||||
@@ -75,7 +75,7 @@ extern int init_r4k_clocksource(void);
|
||||
|
||||
static inline int init_mips_clocksource(void)
|
||||
{
|
||||
#ifdef CONFIG_CSRC_R4K
|
||||
#if defined(CONFIG_CSRC_R4K) && !defined(CONFIG_CSRC_GIC)
|
||||
return init_r4k_clocksource();
|
||||
#else
|
||||
return 0;
|
||||
|
||||
Reference in New Issue
Block a user