Merge branch 'master' of /home/davem/src/GIT/linux-2.6/
Conflicts: drivers/staging/Kconfig drivers/staging/Makefile drivers/staging/cpc-usb/TODO drivers/staging/cpc-usb/cpc-usb_drv.c drivers/staging/cpc-usb/cpc.h drivers/staging/cpc-usb/cpc_int.h drivers/staging/cpc-usb/cpcusb.h
This commit is contained in:
David S. Miller
@@ -24,88 +24,78 @@
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#define USB_SUBCLASS_AUDIOCONTROL 0x01
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#define USB_SUBCLASS_AUDIOSTREAMING 0x02
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#define USB_SUBCLASS_MIDISTREAMING 0x03
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#define USB_SUBCLASS_VENDOR_SPEC 0xff
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/* A.5 Audio Class-Specific AC interface Descriptor Subtypes*/
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#define HEADER 0x01
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#define INPUT_TERMINAL 0x02
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#define OUTPUT_TERMINAL 0x03
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#define MIXER_UNIT 0x04
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#define SELECTOR_UNIT 0x05
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#define FEATURE_UNIT 0x06
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#define PROCESSING_UNIT 0x07
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#define EXTENSION_UNIT 0x08
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/* A.5 Audio Class-Specific AC Interface Descriptor Subtypes */
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#define UAC_HEADER 0x01
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#define UAC_INPUT_TERMINAL 0x02
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#define UAC_OUTPUT_TERMINAL 0x03
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#define UAC_MIXER_UNIT 0x04
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#define UAC_SELECTOR_UNIT 0x05
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#define UAC_FEATURE_UNIT 0x06
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#define UAC_PROCESSING_UNIT 0x07
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#define UAC_EXTENSION_UNIT 0x08
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#define AS_GENERAL 0x01
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#define FORMAT_TYPE 0x02
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#define FORMAT_SPECIFIC 0x03
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/* A.6 Audio Class-Specific AS Interface Descriptor Subtypes */
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#define UAC_AS_GENERAL 0x01
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#define UAC_FORMAT_TYPE 0x02
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#define UAC_FORMAT_SPECIFIC 0x03
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#define EP_GENERAL 0x01
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/* A.8 Audio Class-Specific Endpoint Descriptor Subtypes */
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#define UAC_EP_GENERAL 0x01
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#define MS_GENERAL 0x01
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#define MIDI_IN_JACK 0x02
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#define MIDI_OUT_JACK 0x03
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/* A.9 Audio Class-Specific Request Codes */
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#define UAC_SET_ 0x00
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#define UAC_GET_ 0x80
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/* endpoint attributes */
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#define EP_ATTR_MASK 0x0c
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#define EP_ATTR_ASYNC 0x04
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#define EP_ATTR_ADAPTIVE 0x08
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#define EP_ATTR_SYNC 0x0c
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#define UAC__CUR 0x1
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#define UAC__MIN 0x2
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#define UAC__MAX 0x3
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#define UAC__RES 0x4
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#define UAC__MEM 0x5
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/* cs endpoint attributes */
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#define EP_CS_ATTR_SAMPLE_RATE 0x01
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#define EP_CS_ATTR_PITCH_CONTROL 0x02
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#define EP_CS_ATTR_FILL_MAX 0x80
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#define UAC_SET_CUR (UAC_SET_ | UAC__CUR)
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#define UAC_GET_CUR (UAC_GET_ | UAC__CUR)
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#define UAC_SET_MIN (UAC_SET_ | UAC__MIN)
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#define UAC_GET_MIN (UAC_GET_ | UAC__MIN)
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#define UAC_SET_MAX (UAC_SET_ | UAC__MAX)
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#define UAC_GET_MAX (UAC_GET_ | UAC__MAX)
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#define UAC_SET_RES (UAC_SET_ | UAC__RES)
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#define UAC_GET_RES (UAC_GET_ | UAC__RES)
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#define UAC_SET_MEM (UAC_SET_ | UAC__MEM)
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#define UAC_GET_MEM (UAC_GET_ | UAC__MEM)
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/* Audio Class specific Request Codes */
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#define USB_AUDIO_SET_INTF 0x21
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#define USB_AUDIO_SET_ENDPOINT 0x22
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#define USB_AUDIO_GET_INTF 0xa1
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#define USB_AUDIO_GET_ENDPOINT 0xa2
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#define UAC_GET_STAT 0xff
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#define SET_ 0x00
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#define GET_ 0x80
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/* MIDI - A.1 MS Class-Specific Interface Descriptor Subtypes */
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#define UAC_MS_HEADER 0x01
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#define UAC_MIDI_IN_JACK 0x02
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#define UAC_MIDI_OUT_JACK 0x03
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#define _CUR 0x1
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#define _MIN 0x2
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#define _MAX 0x3
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#define _RES 0x4
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#define _MEM 0x5
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/* MIDI - A.1 MS Class-Specific Endpoint Descriptor Subtypes */
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#define UAC_MS_GENERAL 0x01
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#define SET_CUR (SET_ | _CUR)
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#define GET_CUR (GET_ | _CUR)
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#define SET_MIN (SET_ | _MIN)
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#define GET_MIN (GET_ | _MIN)
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#define SET_MAX (SET_ | _MAX)
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#define GET_MAX (GET_ | _MAX)
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#define SET_RES (SET_ | _RES)
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#define GET_RES (GET_ | _RES)
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#define SET_MEM (SET_ | _MEM)
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#define GET_MEM (GET_ | _MEM)
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#define GET_STAT 0xff
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#define USB_AC_TERMINAL_UNDEFINED 0x100
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#define USB_AC_TERMINAL_STREAMING 0x101
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#define USB_AC_TERMINAL_VENDOR_SPEC 0x1FF
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/* Terminals - 2.1 USB Terminal Types */
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#define UAC_TERMINAL_UNDEFINED 0x100
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#define UAC_TERMINAL_STREAMING 0x101
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#define UAC_TERMINAL_VENDOR_SPEC 0x1FF
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/* Terminal Control Selectors */
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/* 4.3.2 Class-Specific AC Interface Descriptor */
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struct usb_ac_header_descriptor {
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struct uac_ac_header_descriptor {
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__u8 bLength; /* 8 + n */
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__u8 bDescriptorType; /* USB_DT_CS_INTERFACE */
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__u8 bDescriptorSubtype; /* USB_MS_HEADER */
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__u8 bDescriptorSubtype; /* UAC_MS_HEADER */
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__le16 bcdADC; /* 0x0100 */
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__le16 wTotalLength; /* includes Unit and Terminal desc. */
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__u8 bInCollection; /* n */
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__u8 baInterfaceNr[]; /* [n] */
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} __attribute__ ((packed));
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#define USB_DT_AC_HEADER_SIZE(n) (8 + (n))
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#define UAC_DT_AC_HEADER_SIZE(n) (8 + (n))
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/* As above, but more useful for defining your own descriptors: */
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#define DECLARE_USB_AC_HEADER_DESCRIPTOR(n) \
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struct usb_ac_header_descriptor_##n { \
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#define DECLARE_UAC_AC_HEADER_DESCRIPTOR(n) \
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struct uac_ac_header_descriptor_##n { \
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__u8 bLength; \
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__u8 bDescriptorType; \
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__u8 bDescriptorSubtype; \
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@@ -116,7 +106,7 @@ struct usb_ac_header_descriptor_##n { \
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} __attribute__ ((packed))
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/* 4.3.2.1 Input Terminal Descriptor */
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struct usb_input_terminal_descriptor {
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struct uac_input_terminal_descriptor {
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__u8 bLength; /* in bytes: 12 */
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__u8 bDescriptorType; /* CS_INTERFACE descriptor type */
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__u8 bDescriptorSubtype; /* INPUT_TERMINAL descriptor subtype */
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@@ -129,18 +119,19 @@ struct usb_input_terminal_descriptor {
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__u8 iTerminal;
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} __attribute__ ((packed));
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#define USB_DT_AC_INPUT_TERMINAL_SIZE 12
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#define UAC_DT_INPUT_TERMINAL_SIZE 12
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#define USB_AC_INPUT_TERMINAL_UNDEFINED 0x200
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#define USB_AC_INPUT_TERMINAL_MICROPHONE 0x201
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#define USB_AC_INPUT_TERMINAL_DESKTOP_MICROPHONE 0x202
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#define USB_AC_INPUT_TERMINAL_PERSONAL_MICROPHONE 0x203
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#define USB_AC_INPUT_TERMINAL_OMNI_DIR_MICROPHONE 0x204
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#define USB_AC_INPUT_TERMINAL_MICROPHONE_ARRAY 0x205
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#define USB_AC_INPUT_TERMINAL_PROC_MICROPHONE_ARRAY 0x206
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/* Terminals - 2.2 Input Terminal Types */
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#define UAC_INPUT_TERMINAL_UNDEFINED 0x200
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#define UAC_INPUT_TERMINAL_MICROPHONE 0x201
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#define UAC_INPUT_TERMINAL_DESKTOP_MICROPHONE 0x202
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#define UAC_INPUT_TERMINAL_PERSONAL_MICROPHONE 0x203
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#define UAC_INPUT_TERMINAL_OMNI_DIR_MICROPHONE 0x204
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#define UAC_INPUT_TERMINAL_MICROPHONE_ARRAY 0x205
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#define UAC_INPUT_TERMINAL_PROC_MICROPHONE_ARRAY 0x206
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/* 4.3.2.2 Output Terminal Descriptor */
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struct usb_output_terminal_descriptor {
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struct uac_output_terminal_descriptor {
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__u8 bLength; /* in bytes: 9 */
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__u8 bDescriptorType; /* CS_INTERFACE descriptor type */
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__u8 bDescriptorSubtype; /* OUTPUT_TERMINAL descriptor subtype */
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@@ -151,23 +142,24 @@ struct usb_output_terminal_descriptor {
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__u8 iTerminal;
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} __attribute__ ((packed));
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#define USB_DT_AC_OUTPUT_TERMINAL_SIZE 9
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#define UAC_DT_OUTPUT_TERMINAL_SIZE 9
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#define USB_AC_OUTPUT_TERMINAL_UNDEFINED 0x300
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#define USB_AC_OUTPUT_TERMINAL_SPEAKER 0x301
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#define USB_AC_OUTPUT_TERMINAL_HEADPHONES 0x302
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#define USB_AC_OUTPUT_TERMINAL_HEAD_MOUNTED_DISPLAY_AUDIO 0x303
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#define USB_AC_OUTPUT_TERMINAL_DESKTOP_SPEAKER 0x304
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#define USB_AC_OUTPUT_TERMINAL_ROOM_SPEAKER 0x305
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#define USB_AC_OUTPUT_TERMINAL_COMMUNICATION_SPEAKER 0x306
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#define USB_AC_OUTPUT_TERMINAL_LOW_FREQ_EFFECTS_SPEAKER 0x307
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/* Terminals - 2.3 Output Terminal Types */
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#define UAC_OUTPUT_TERMINAL_UNDEFINED 0x300
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#define UAC_OUTPUT_TERMINAL_SPEAKER 0x301
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#define UAC_OUTPUT_TERMINAL_HEADPHONES 0x302
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#define UAC_OUTPUT_TERMINAL_HEAD_MOUNTED_DISPLAY_AUDIO 0x303
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#define UAC_OUTPUT_TERMINAL_DESKTOP_SPEAKER 0x304
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#define UAC_OUTPUT_TERMINAL_ROOM_SPEAKER 0x305
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#define UAC_OUTPUT_TERMINAL_COMMUNICATION_SPEAKER 0x306
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#define UAC_OUTPUT_TERMINAL_LOW_FREQ_EFFECTS_SPEAKER 0x307
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/* Set bControlSize = 2 as default setting */
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#define USB_DT_AC_FEATURE_UNIT_SIZE(ch) (7 + ((ch) + 1) * 2)
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#define UAC_DT_FEATURE_UNIT_SIZE(ch) (7 + ((ch) + 1) * 2)
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/* As above, but more useful for defining your own descriptors: */
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#define DECLARE_USB_AC_FEATURE_UNIT_DESCRIPTOR(ch) \
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struct usb_ac_feature_unit_descriptor_##ch { \
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#define DECLARE_UAC_FEATURE_UNIT_DESCRIPTOR(ch) \
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struct uac_feature_unit_descriptor_##ch { \
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__u8 bLength; \
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__u8 bDescriptorType; \
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__u8 bDescriptorSubtype; \
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@@ -179,7 +171,7 @@ struct usb_ac_feature_unit_descriptor_##ch { \
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} __attribute__ ((packed))
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/* 4.5.2 Class-Specific AS Interface Descriptor */
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struct usb_as_header_descriptor {
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struct uac_as_header_descriptor {
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__u8 bLength; /* in bytes: 7 */
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__u8 bDescriptorType; /* USB_DT_CS_INTERFACE */
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__u8 bDescriptorSubtype; /* AS_GENERAL */
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@@ -188,16 +180,17 @@ struct usb_as_header_descriptor {
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__le16 wFormatTag; /* The Audio Data Format */
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} __attribute__ ((packed));
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#define USB_DT_AS_HEADER_SIZE 7
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#define UAC_DT_AS_HEADER_SIZE 7
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#define USB_AS_AUDIO_FORMAT_TYPE_I_UNDEFINED 0x0
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#define USB_AS_AUDIO_FORMAT_TYPE_I_PCM 0x1
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#define USB_AS_AUDIO_FORMAT_TYPE_I_PCM8 0x2
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#define USB_AS_AUDIO_FORMAT_TYPE_I_IEEE_FLOAT 0x3
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#define USB_AS_AUDIO_FORMAT_TYPE_I_ALAW 0x4
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#define USB_AS_AUDIO_FORMAT_TYPE_I_MULAW 0x5
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/* Formats - A.1.1 Audio Data Format Type I Codes */
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#define UAC_FORMAT_TYPE_I_UNDEFINED 0x0
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#define UAC_FORMAT_TYPE_I_PCM 0x1
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#define UAC_FORMAT_TYPE_I_PCM8 0x2
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#define UAC_FORMAT_TYPE_I_IEEE_FLOAT 0x3
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#define UAC_FORMAT_TYPE_I_ALAW 0x4
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#define UAC_FORMAT_TYPE_I_MULAW 0x5
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struct usb_as_format_type_i_continuous_descriptor {
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struct uac_format_type_i_continuous_descriptor {
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__u8 bLength; /* in bytes: 8 + (ns * 3) */
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__u8 bDescriptorType; /* USB_DT_CS_INTERFACE */
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__u8 bDescriptorSubtype; /* FORMAT_TYPE */
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@@ -210,9 +203,9 @@ struct usb_as_format_type_i_continuous_descriptor {
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__u8 tUpperSamFreq[3];
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} __attribute__ ((packed));
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#define USB_AS_FORMAT_TYPE_I_CONTINUOUS_DESC_SIZE 14
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#define UAC_FORMAT_TYPE_I_CONTINUOUS_DESC_SIZE 14
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struct usb_as_formate_type_i_discrete_descriptor {
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struct uac_format_type_i_discrete_descriptor {
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__u8 bLength; /* in bytes: 8 + (ns * 3) */
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__u8 bDescriptorType; /* USB_DT_CS_INTERFACE */
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__u8 bDescriptorSubtype; /* FORMAT_TYPE */
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@@ -224,8 +217,8 @@ struct usb_as_formate_type_i_discrete_descriptor {
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__u8 tSamFreq[][3];
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} __attribute__ ((packed));
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#define DECLARE_USB_AS_FORMAT_TYPE_I_DISCRETE_DESC(n) \
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struct usb_as_formate_type_i_discrete_descriptor_##n { \
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#define DECLARE_UAC_FORMAT_TYPE_I_DISCRETE_DESC(n) \
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struct uac_format_type_i_discrete_descriptor_##n { \
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__u8 bLength; \
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__u8 bDescriptorType; \
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__u8 bDescriptorSubtype; \
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@@ -237,18 +230,15 @@ struct usb_as_formate_type_i_discrete_descriptor_##n { \
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__u8 tSamFreq[n][3]; \
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} __attribute__ ((packed))
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#define USB_AS_FORMAT_TYPE_I_DISCRETE_DESC_SIZE(n) (8 + (n * 3))
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#define UAC_FORMAT_TYPE_I_DISCRETE_DESC_SIZE(n) (8 + (n * 3))
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#define USB_AS_FORMAT_TYPE_UNDEFINED 0x0
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#define USB_AS_FORMAT_TYPE_I 0x1
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#define USB_AS_FORMAT_TYPE_II 0x2
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#define USB_AS_FORMAT_TYPE_III 0x3
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/* Formats - A.2 Format Type Codes */
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#define UAC_FORMAT_TYPE_UNDEFINED 0x0
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#define UAC_FORMAT_TYPE_I 0x1
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#define UAC_FORMAT_TYPE_II 0x2
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#define UAC_FORMAT_TYPE_III 0x3
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#define USB_AS_ENDPOINT_ASYNC (1 << 2)
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#define USB_AS_ENDPOINT_ADAPTIVE (2 << 2)
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#define USB_AS_ENDPOINT_SYNC (3 << 2)
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struct usb_as_iso_endpoint_descriptor {
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struct uac_iso_endpoint_descriptor {
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__u8 bLength; /* in bytes: 7 */
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__u8 bDescriptorType; /* USB_DT_CS_ENDPOINT */
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__u8 bDescriptorSubtype; /* EP_GENERAL */
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@@ -256,30 +246,37 @@ struct usb_as_iso_endpoint_descriptor {
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__u8 bLockDelayUnits;
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__le16 wLockDelay;
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};
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#define USB_AS_ISO_ENDPOINT_DESC_SIZE 7
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#define UAC_ISO_ENDPOINT_DESC_SIZE 7
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||||
#define FU_CONTROL_UNDEFINED 0x00
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#define MUTE_CONTROL 0x01
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||||
#define VOLUME_CONTROL 0x02
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#define BASS_CONTROL 0x03
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||||
#define MID_CONTROL 0x04
|
||||
#define TREBLE_CONTROL 0x05
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||||
#define GRAPHIC_EQUALIZER_CONTROL 0x06
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#define AUTOMATIC_GAIN_CONTROL 0x07
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#define DELAY_CONTROL 0x08
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#define BASS_BOOST_CONTROL 0x09
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||||
#define LOUDNESS_CONTROL 0x0a
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#define UAC_EP_CS_ATTR_SAMPLE_RATE 0x01
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#define UAC_EP_CS_ATTR_PITCH_CONTROL 0x02
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#define UAC_EP_CS_ATTR_FILL_MAX 0x80
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||||
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||||
#define FU_MUTE (1 << (MUTE_CONTROL - 1))
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||||
#define FU_VOLUME (1 << (VOLUME_CONTROL - 1))
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||||
#define FU_BASS (1 << (BASS_CONTROL - 1))
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||||
#define FU_MID (1 << (MID_CONTROL - 1))
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||||
#define FU_TREBLE (1 << (TREBLE_CONTROL - 1))
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||||
#define FU_GRAPHIC_EQ (1 << (GRAPHIC_EQUALIZER_CONTROL - 1))
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||||
#define FU_AUTO_GAIN (1 << (AUTOMATIC_GAIN_CONTROL - 1))
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||||
#define FU_DELAY (1 << (DELAY_CONTROL - 1))
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||||
#define FU_BASS_BOOST (1 << (BASS_BOOST_CONTROL - 1))
|
||||
#define FU_LOUDNESS (1 << (LOUDNESS_CONTROL - 1))
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||||
/* A.10.2 Feature Unit Control Selectors */
|
||||
#define UAC_FU_CONTROL_UNDEFINED 0x00
|
||||
#define UAC_MUTE_CONTROL 0x01
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||||
#define UAC_VOLUME_CONTROL 0x02
|
||||
#define UAC_BASS_CONTROL 0x03
|
||||
#define UAC_MID_CONTROL 0x04
|
||||
#define UAC_TREBLE_CONTROL 0x05
|
||||
#define UAC_GRAPHIC_EQUALIZER_CONTROL 0x06
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||||
#define UAC_AUTOMATIC_GAIN_CONTROL 0x07
|
||||
#define UAC_DELAY_CONTROL 0x08
|
||||
#define UAC_BASS_BOOST_CONTROL 0x09
|
||||
#define UAC_LOUDNESS_CONTROL 0x0a
|
||||
|
||||
#define UAC_FU_MUTE (1 << (UAC_MUTE_CONTROL - 1))
|
||||
#define UAC_FU_VOLUME (1 << (UAC_VOLUME_CONTROL - 1))
|
||||
#define UAC_FU_BASS (1 << (UAC_BASS_CONTROL - 1))
|
||||
#define UAC_FU_MID (1 << (UAC_MID_CONTROL - 1))
|
||||
#define UAC_FU_TREBLE (1 << (UAC_TREBLE_CONTROL - 1))
|
||||
#define UAC_FU_GRAPHIC_EQ (1 << (UAC_GRAPHIC_EQUALIZER_CONTROL - 1))
|
||||
#define UAC_FU_AUTO_GAIN (1 << (UAC_AUTOMATIC_GAIN_CONTROL - 1))
|
||||
#define UAC_FU_DELAY (1 << (UAC_DELAY_CONTROL - 1))
|
||||
#define UAC_FU_BASS_BOOST (1 << (UAC_BASS_BOOST_CONTROL - 1))
|
||||
#define UAC_FU_LOUDNESS (1 << (UAC_LOUDNESS_CONTROL - 1))
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
struct usb_audio_control {
|
||||
struct list_head list;
|
||||
@@ -290,18 +287,6 @@ struct usb_audio_control {
|
||||
int (*get)(struct usb_audio_control *con, u8 cmd);
|
||||
};
|
||||
|
||||
static inline int generic_set_cmd(struct usb_audio_control *con, u8 cmd, int value)
|
||||
{
|
||||
con->data[cmd] = value;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int generic_get_cmd(struct usb_audio_control *con, u8 cmd)
|
||||
{
|
||||
return con->data[cmd];
|
||||
}
|
||||
|
||||
struct usb_audio_control_selector {
|
||||
struct list_head list;
|
||||
struct list_head control;
|
||||
@@ -311,4 +296,6 @@ struct usb_audio_control_selector {
|
||||
struct usb_descriptor_header *desc;
|
||||
};
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* __LINUX_USB_AUDIO_H */
|
||||
|
||||
@@ -258,6 +258,8 @@ struct usb_device_descriptor {
|
||||
#define USB_CLASS_APP_SPEC 0xfe
|
||||
#define USB_CLASS_VENDOR_SPEC 0xff
|
||||
|
||||
#define USB_SUBCLASS_VENDOR_SPEC 0xff
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
/* USB_DT_CONFIG: Configuration descriptor information.
|
||||
@@ -348,6 +350,12 @@ struct usb_endpoint_descriptor {
|
||||
#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */
|
||||
#define USB_ENDPOINT_DIR_MASK 0x80
|
||||
|
||||
#define USB_ENDPOINT_SYNCTYPE 0x0c
|
||||
#define USB_ENDPOINT_SYNC_NONE (0 << 2)
|
||||
#define USB_ENDPOINT_SYNC_ASYNC (1 << 2)
|
||||
#define USB_ENDPOINT_SYNC_ADAPTIVE (2 << 2)
|
||||
#define USB_ENDPOINT_SYNC_SYNC (3 << 2)
|
||||
|
||||
#define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */
|
||||
#define USB_ENDPOINT_XFER_CONTROL 0
|
||||
#define USB_ENDPOINT_XFER_ISOC 1
|
||||
|
||||
@@ -105,6 +105,7 @@ struct ehci_regs {
|
||||
#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
|
||||
#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
|
||||
/* 19:16 for port testing */
|
||||
#define PORT_TEST_PKT (0x4<<16) /* Port Test Control - packet test */
|
||||
#define PORT_LED_OFF (0<<14)
|
||||
#define PORT_LED_AMBER (1<<14)
|
||||
#define PORT_LED_GREEN (2<<14)
|
||||
@@ -132,6 +133,19 @@ struct ehci_regs {
|
||||
#define USBMODE_CM_HC (3<<0) /* host controller mode */
|
||||
#define USBMODE_CM_IDLE (0<<0) /* idle state */
|
||||
|
||||
/* Moorestown has some non-standard registers, partially due to the fact that
|
||||
* its EHCI controller has both TT and LPM support. HOSTPCx are extentions to
|
||||
* PORTSCx
|
||||
*/
|
||||
#define HOSTPC0 0x84 /* HOSTPC extension */
|
||||
#define HOSTPC_PHCD (1<<22) /* Phy clock disable */
|
||||
#define HOSTPC_PSPD (3<<25) /* Port speed detection */
|
||||
#define USBMODE_EX 0xc8 /* USB Device mode extension */
|
||||
#define USBMODE_EX_VBPS (1<<5) /* VBus Power Select On */
|
||||
#define USBMODE_EX_HC (3<<0) /* host controller mode */
|
||||
#define TXFILLTUNING 0x24 /* TX FIFO Tuning register */
|
||||
#define TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */
|
||||
|
||||
/* Appendix C, Debug port ... intended for use with special "debug devices"
|
||||
* that can help if there's no serial console. (nonstandard enumeration.)
|
||||
*/
|
||||
@@ -157,4 +171,25 @@ struct ehci_dbg_port {
|
||||
#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep))
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#ifdef CONFIG_EARLY_PRINTK_DBGP
|
||||
#include <linux/init.h>
|
||||
extern int __init early_dbgp_init(char *s);
|
||||
extern struct console early_dbgp_console;
|
||||
#endif /* CONFIG_EARLY_PRINTK_DBGP */
|
||||
|
||||
#ifdef CONFIG_EARLY_PRINTK_DBGP
|
||||
/* Call backs from ehci host driver to ehci debug driver */
|
||||
extern int dbgp_external_startup(void);
|
||||
extern int dbgp_reset_prep(void);
|
||||
#else
|
||||
static inline int dbgp_reset_prep(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
static inline int dbgp_external_startup(void)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __LINUX_USB_EHCI_DEF_H */
|
||||
|
||||
46
include/linux/usb/isp1362.h
Normal file
46
include/linux/usb/isp1362.h
Normal file
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* board initialization code should put one of these into dev->platform_data
|
||||
* and place the isp1362 onto platform_bus.
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_USB_ISP1362_H__
|
||||
#define __LINUX_USB_ISP1362_H__
|
||||
|
||||
struct isp1362_platform_data {
|
||||
/* Enable internal pulldown resistors on downstream ports */
|
||||
unsigned sel15Kres:1;
|
||||
/* Clock cannot be stopped */
|
||||
unsigned clknotstop:1;
|
||||
/* On-chip overcurrent protection */
|
||||
unsigned oc_enable:1;
|
||||
/* INT output polarity */
|
||||
unsigned int_act_high:1;
|
||||
/* INT edge or level triggered */
|
||||
unsigned int_edge_triggered:1;
|
||||
/* DREQ output polarity */
|
||||
unsigned dreq_act_high:1;
|
||||
/* DACK input polarity */
|
||||
unsigned dack_act_high:1;
|
||||
/* chip can be resumed via H_WAKEUP pin */
|
||||
unsigned remote_wakeup_connected:1;
|
||||
/* Switch or not to switch (keep always powered) */
|
||||
unsigned no_power_switching:1;
|
||||
/* Ganged port power switching (0) or individual port power switching (1) */
|
||||
unsigned power_switching_mode:1;
|
||||
/* Given port_power, msec/2 after power on till power good */
|
||||
u8 potpg;
|
||||
/* Hardware reset set/clear */
|
||||
void (*reset) (struct device *dev, int set);
|
||||
/* Clock start/stop */
|
||||
void (*clock) (struct device *dev, int start);
|
||||
/* Inter-io delay (ns). The chip is picky about access timings; it
|
||||
* expects at least:
|
||||
* 110ns delay between consecutive accesses to DATA_REG,
|
||||
* 300ns delay between access to ADDR_REG and DATA_REG (registers)
|
||||
* 462ns delay between access to ADDR_REG and DATA_REG (buffer memory)
|
||||
* WE MUST NOT be activated during these intervals (even without CS!)
|
||||
*/
|
||||
void (*delay) (struct device *dev, unsigned int delay);
|
||||
};
|
||||
|
||||
#endif
|
||||
18
include/linux/usb/isp1760.h
Normal file
18
include/linux/usb/isp1760.h
Normal file
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* board initialization should put one of these into dev->platform_data
|
||||
* and place the isp1760 onto platform_bus named "isp1760-hcd".
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_USB_ISP1760_H
|
||||
#define __LINUX_USB_ISP1760_H
|
||||
|
||||
struct isp1760_platform_data {
|
||||
unsigned is_isp1761:1; /* Chip is ISP1761 */
|
||||
unsigned bus_width_16:1; /* 16/32-bit data bus width */
|
||||
unsigned port1_otg:1; /* Port 1 supports OTG */
|
||||
unsigned analog_oc:1; /* Analog overcurrent */
|
||||
unsigned dack_polarity_high:1; /* DACK active high */
|
||||
unsigned dreq_polarity_high:1; /* DREQ active high */
|
||||
};
|
||||
|
||||
#endif /* __LINUX_USB_ISP1760_H */
|
||||
44
include/linux/usb/m66592.h
Normal file
44
include/linux/usb/m66592.h
Normal file
@@ -0,0 +1,44 @@
|
||||
/*
|
||||
* M66592 driver platform data
|
||||
*
|
||||
* Copyright (C) 2009 Renesas Solutions Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_USB_M66592_H
|
||||
#define __LINUX_USB_M66592_H
|
||||
|
||||
#define M66592_PLATDATA_XTAL_12MHZ 0x01
|
||||
#define M66592_PLATDATA_XTAL_24MHZ 0x02
|
||||
#define M66592_PLATDATA_XTAL_48MHZ 0x03
|
||||
|
||||
struct m66592_platdata {
|
||||
/* one = on chip controller, zero = external controller */
|
||||
unsigned on_chip:1;
|
||||
|
||||
/* one = big endian, zero = little endian */
|
||||
unsigned endian:1;
|
||||
|
||||
/* (external controller only) M66592_PLATDATA_XTAL_nnMHZ */
|
||||
unsigned xtal:2;
|
||||
|
||||
/* (external controller only) one = 3.3V, zero = 1.5V */
|
||||
unsigned vif:1;
|
||||
|
||||
};
|
||||
|
||||
#endif /* __LINUX_USB_M66592_H */
|
||||
|
||||
@@ -28,9 +28,12 @@
|
||||
#define R8A66597_PLATDATA_XTAL_48MHZ 0x03
|
||||
|
||||
struct r8a66597_platdata {
|
||||
/* This ops can controll port power instead of DVSTCTR register. */
|
||||
/* This callback can control port power instead of DVSTCTR register. */
|
||||
void (*port_power)(int port, int power);
|
||||
|
||||
/* set one = on chip controller, set zero = external controller */
|
||||
unsigned on_chip:1;
|
||||
|
||||
/* (external controller only) set R8A66597_PLATDATA_XTAL_nnMHZ */
|
||||
unsigned xtal:2;
|
||||
|
||||
@@ -40,5 +43,373 @@ struct r8a66597_platdata {
|
||||
/* set one = big endian, set zero = little endian */
|
||||
unsigned endian:1;
|
||||
};
|
||||
#endif
|
||||
|
||||
/* Register definitions */
|
||||
#define SYSCFG0 0x00
|
||||
#define SYSCFG1 0x02
|
||||
#define SYSSTS0 0x04
|
||||
#define SYSSTS1 0x06
|
||||
#define DVSTCTR0 0x08
|
||||
#define DVSTCTR1 0x0A
|
||||
#define TESTMODE 0x0C
|
||||
#define PINCFG 0x0E
|
||||
#define DMA0CFG 0x10
|
||||
#define DMA1CFG 0x12
|
||||
#define CFIFO 0x14
|
||||
#define D0FIFO 0x18
|
||||
#define D1FIFO 0x1C
|
||||
#define CFIFOSEL 0x20
|
||||
#define CFIFOCTR 0x22
|
||||
#define CFIFOSIE 0x24
|
||||
#define D0FIFOSEL 0x28
|
||||
#define D0FIFOCTR 0x2A
|
||||
#define D1FIFOSEL 0x2C
|
||||
#define D1FIFOCTR 0x2E
|
||||
#define INTENB0 0x30
|
||||
#define INTENB1 0x32
|
||||
#define INTENB2 0x34
|
||||
#define BRDYENB 0x36
|
||||
#define NRDYENB 0x38
|
||||
#define BEMPENB 0x3A
|
||||
#define SOFCFG 0x3C
|
||||
#define INTSTS0 0x40
|
||||
#define INTSTS1 0x42
|
||||
#define INTSTS2 0x44
|
||||
#define BRDYSTS 0x46
|
||||
#define NRDYSTS 0x48
|
||||
#define BEMPSTS 0x4A
|
||||
#define FRMNUM 0x4C
|
||||
#define UFRMNUM 0x4E
|
||||
#define USBADDR 0x50
|
||||
#define USBREQ 0x54
|
||||
#define USBVAL 0x56
|
||||
#define USBINDX 0x58
|
||||
#define USBLENG 0x5A
|
||||
#define DCPCFG 0x5C
|
||||
#define DCPMAXP 0x5E
|
||||
#define DCPCTR 0x60
|
||||
#define PIPESEL 0x64
|
||||
#define PIPECFG 0x68
|
||||
#define PIPEBUF 0x6A
|
||||
#define PIPEMAXP 0x6C
|
||||
#define PIPEPERI 0x6E
|
||||
#define PIPE1CTR 0x70
|
||||
#define PIPE2CTR 0x72
|
||||
#define PIPE3CTR 0x74
|
||||
#define PIPE4CTR 0x76
|
||||
#define PIPE5CTR 0x78
|
||||
#define PIPE6CTR 0x7A
|
||||
#define PIPE7CTR 0x7C
|
||||
#define PIPE8CTR 0x7E
|
||||
#define PIPE9CTR 0x80
|
||||
#define PIPE1TRE 0x90
|
||||
#define PIPE1TRN 0x92
|
||||
#define PIPE2TRE 0x94
|
||||
#define PIPE2TRN 0x96
|
||||
#define PIPE3TRE 0x98
|
||||
#define PIPE3TRN 0x9A
|
||||
#define PIPE4TRE 0x9C
|
||||
#define PIPE4TRN 0x9E
|
||||
#define PIPE5TRE 0xA0
|
||||
#define PIPE5TRN 0xA2
|
||||
#define DEVADD0 0xD0
|
||||
#define DEVADD1 0xD2
|
||||
#define DEVADD2 0xD4
|
||||
#define DEVADD3 0xD6
|
||||
#define DEVADD4 0xD8
|
||||
#define DEVADD5 0xDA
|
||||
#define DEVADD6 0xDC
|
||||
#define DEVADD7 0xDE
|
||||
#define DEVADD8 0xE0
|
||||
#define DEVADD9 0xE2
|
||||
#define DEVADDA 0xE4
|
||||
|
||||
/* System Configuration Control Register */
|
||||
#define XTAL 0xC000 /* b15-14: Crystal selection */
|
||||
#define XTAL48 0x8000 /* 48MHz */
|
||||
#define XTAL24 0x4000 /* 24MHz */
|
||||
#define XTAL12 0x0000 /* 12MHz */
|
||||
#define XCKE 0x2000 /* b13: External clock enable */
|
||||
#define PLLC 0x0800 /* b11: PLL control */
|
||||
#define SCKE 0x0400 /* b10: USB clock enable */
|
||||
#define PCSDIS 0x0200 /* b9: not CS wakeup */
|
||||
#define LPSME 0x0100 /* b8: Low power sleep mode */
|
||||
#define HSE 0x0080 /* b7: Hi-speed enable */
|
||||
#define DCFM 0x0040 /* b6: Controller function select */
|
||||
#define DRPD 0x0020 /* b5: D+/- pull down control */
|
||||
#define DPRPU 0x0010 /* b4: D+ pull up control */
|
||||
#define USBE 0x0001 /* b0: USB module operation enable */
|
||||
|
||||
/* System Configuration Status Register */
|
||||
#define OVCBIT 0x8000 /* b15-14: Over-current bit */
|
||||
#define OVCMON 0xC000 /* b15-14: Over-current monitor */
|
||||
#define SOFEA 0x0020 /* b5: SOF monitor */
|
||||
#define IDMON 0x0004 /* b3: ID-pin monitor */
|
||||
#define LNST 0x0003 /* b1-0: D+, D- line status */
|
||||
#define SE1 0x0003 /* SE1 */
|
||||
#define FS_KSTS 0x0002 /* Full-Speed K State */
|
||||
#define FS_JSTS 0x0001 /* Full-Speed J State */
|
||||
#define LS_JSTS 0x0002 /* Low-Speed J State */
|
||||
#define LS_KSTS 0x0001 /* Low-Speed K State */
|
||||
#define SE0 0x0000 /* SE0 */
|
||||
|
||||
/* Device State Control Register */
|
||||
#define EXTLP0 0x0400 /* b10: External port */
|
||||
#define VBOUT 0x0200 /* b9: VBUS output */
|
||||
#define WKUP 0x0100 /* b8: Remote wakeup */
|
||||
#define RWUPE 0x0080 /* b7: Remote wakeup sense */
|
||||
#define USBRST 0x0040 /* b6: USB reset enable */
|
||||
#define RESUME 0x0020 /* b5: Resume enable */
|
||||
#define UACT 0x0010 /* b4: USB bus enable */
|
||||
#define RHST 0x0007 /* b1-0: Reset handshake status */
|
||||
#define HSPROC 0x0004 /* HS handshake is processing */
|
||||
#define HSMODE 0x0003 /* Hi-Speed mode */
|
||||
#define FSMODE 0x0002 /* Full-Speed mode */
|
||||
#define LSMODE 0x0001 /* Low-Speed mode */
|
||||
#define UNDECID 0x0000 /* Undecided */
|
||||
|
||||
/* Test Mode Register */
|
||||
#define UTST 0x000F /* b3-0: Test select */
|
||||
#define H_TST_PACKET 0x000C /* HOST TEST Packet */
|
||||
#define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
|
||||
#define H_TST_K 0x000A /* HOST TEST K */
|
||||
#define H_TST_J 0x0009 /* HOST TEST J */
|
||||
#define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
|
||||
#define P_TST_PACKET 0x0004 /* PERI TEST Packet */
|
||||
#define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
|
||||
#define P_TST_K 0x0002 /* PERI TEST K */
|
||||
#define P_TST_J 0x0001 /* PERI TEST J */
|
||||
#define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
|
||||
|
||||
/* Data Pin Configuration Register */
|
||||
#define LDRV 0x8000 /* b15: Drive Current Adjust */
|
||||
#define VIF1 0x0000 /* VIF = 1.8V */
|
||||
#define VIF3 0x8000 /* VIF = 3.3V */
|
||||
#define INTA 0x0001 /* b1: USB INT-pin active */
|
||||
|
||||
/* DMAx Pin Configuration Register */
|
||||
#define DREQA 0x4000 /* b14: Dreq active select */
|
||||
#define BURST 0x2000 /* b13: Burst mode */
|
||||
#define DACKA 0x0400 /* b10: Dack active select */
|
||||
#define DFORM 0x0380 /* b9-7: DMA mode select */
|
||||
#define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
|
||||
#define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
|
||||
#define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
|
||||
#define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
|
||||
#define DENDA 0x0040 /* b6: Dend active select */
|
||||
#define PKTM 0x0020 /* b5: Packet mode */
|
||||
#define DENDE 0x0010 /* b4: Dend enable */
|
||||
#define OBUS 0x0004 /* b2: OUTbus mode */
|
||||
|
||||
/* CFIFO/DxFIFO Port Select Register */
|
||||
#define RCNT 0x8000 /* b15: Read count mode */
|
||||
#define REW 0x4000 /* b14: Buffer rewind */
|
||||
#define DCLRM 0x2000 /* b13: DMA buffer clear mode */
|
||||
#define DREQE 0x1000 /* b12: DREQ output enable */
|
||||
#define MBW_8 0x0000 /* 8bit */
|
||||
#define MBW_16 0x0400 /* 16bit */
|
||||
#define MBW_32 0x0800 /* 32bit */
|
||||
#define BIGEND 0x0100 /* b8: Big endian mode */
|
||||
#define BYTE_LITTLE 0x0000 /* little dendian */
|
||||
#define BYTE_BIG 0x0100 /* big endifan */
|
||||
#define ISEL 0x0020 /* b5: DCP FIFO port direction select */
|
||||
#define CURPIPE 0x000F /* b2-0: PIPE select */
|
||||
|
||||
/* CFIFO/DxFIFO Port Control Register */
|
||||
#define BVAL 0x8000 /* b15: Buffer valid flag */
|
||||
#define BCLR 0x4000 /* b14: Buffer clear */
|
||||
#define FRDY 0x2000 /* b13: FIFO ready */
|
||||
#define DTLN 0x0FFF /* b11-0: FIFO received data length */
|
||||
|
||||
/* Interrupt Enable Register 0 */
|
||||
#define VBSE 0x8000 /* b15: VBUS interrupt */
|
||||
#define RSME 0x4000 /* b14: Resume interrupt */
|
||||
#define SOFE 0x2000 /* b13: Frame update interrupt */
|
||||
#define DVSE 0x1000 /* b12: Device state transition interrupt */
|
||||
#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
|
||||
#define BEMPE 0x0400 /* b10: Buffer empty interrupt */
|
||||
#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
|
||||
#define BRDYE 0x0100 /* b8: Buffer ready interrupt */
|
||||
|
||||
/* Interrupt Enable Register 1 */
|
||||
#define OVRCRE 0x8000 /* b15: Over-current interrupt */
|
||||
#define BCHGE 0x4000 /* b14: USB us chenge interrupt */
|
||||
#define DTCHE 0x1000 /* b12: Detach sense interrupt */
|
||||
#define ATTCHE 0x0800 /* b11: Attach sense interrupt */
|
||||
#define EOFERRE 0x0040 /* b6: EOF error interrupt */
|
||||
#define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
|
||||
#define SACKE 0x0010 /* b4: SETUP ACK interrupt */
|
||||
|
||||
/* BRDY Interrupt Enable/Status Register */
|
||||
#define BRDY9 0x0200 /* b9: PIPE9 */
|
||||
#define BRDY8 0x0100 /* b8: PIPE8 */
|
||||
#define BRDY7 0x0080 /* b7: PIPE7 */
|
||||
#define BRDY6 0x0040 /* b6: PIPE6 */
|
||||
#define BRDY5 0x0020 /* b5: PIPE5 */
|
||||
#define BRDY4 0x0010 /* b4: PIPE4 */
|
||||
#define BRDY3 0x0008 /* b3: PIPE3 */
|
||||
#define BRDY2 0x0004 /* b2: PIPE2 */
|
||||
#define BRDY1 0x0002 /* b1: PIPE1 */
|
||||
#define BRDY0 0x0001 /* b1: PIPE0 */
|
||||
|
||||
/* NRDY Interrupt Enable/Status Register */
|
||||
#define NRDY9 0x0200 /* b9: PIPE9 */
|
||||
#define NRDY8 0x0100 /* b8: PIPE8 */
|
||||
#define NRDY7 0x0080 /* b7: PIPE7 */
|
||||
#define NRDY6 0x0040 /* b6: PIPE6 */
|
||||
#define NRDY5 0x0020 /* b5: PIPE5 */
|
||||
#define NRDY4 0x0010 /* b4: PIPE4 */
|
||||
#define NRDY3 0x0008 /* b3: PIPE3 */
|
||||
#define NRDY2 0x0004 /* b2: PIPE2 */
|
||||
#define NRDY1 0x0002 /* b1: PIPE1 */
|
||||
#define NRDY0 0x0001 /* b1: PIPE0 */
|
||||
|
||||
/* BEMP Interrupt Enable/Status Register */
|
||||
#define BEMP9 0x0200 /* b9: PIPE9 */
|
||||
#define BEMP8 0x0100 /* b8: PIPE8 */
|
||||
#define BEMP7 0x0080 /* b7: PIPE7 */
|
||||
#define BEMP6 0x0040 /* b6: PIPE6 */
|
||||
#define BEMP5 0x0020 /* b5: PIPE5 */
|
||||
#define BEMP4 0x0010 /* b4: PIPE4 */
|
||||
#define BEMP3 0x0008 /* b3: PIPE3 */
|
||||
#define BEMP2 0x0004 /* b2: PIPE2 */
|
||||
#define BEMP1 0x0002 /* b1: PIPE1 */
|
||||
#define BEMP0 0x0001 /* b0: PIPE0 */
|
||||
|
||||
/* SOF Pin Configuration Register */
|
||||
#define TRNENSEL 0x0100 /* b8: Select transaction enable period */
|
||||
#define BRDYM 0x0040 /* b6: BRDY clear timing */
|
||||
#define INTL 0x0020 /* b5: Interrupt sense select */
|
||||
#define EDGESTS 0x0010 /* b4: */
|
||||
#define SOFMODE 0x000C /* b3-2: SOF pin select */
|
||||
#define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
|
||||
#define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
|
||||
#define SOF_DISABLE 0x0000 /* SOF OUT Disable */
|
||||
|
||||
/* Interrupt Status Register 0 */
|
||||
#define VBINT 0x8000 /* b15: VBUS interrupt */
|
||||
#define RESM 0x4000 /* b14: Resume interrupt */
|
||||
#define SOFR 0x2000 /* b13: SOF frame update interrupt */
|
||||
#define DVST 0x1000 /* b12: Device state transition interrupt */
|
||||
#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
|
||||
#define BEMP 0x0400 /* b10: Buffer empty interrupt */
|
||||
#define NRDY 0x0200 /* b9: Buffer not ready interrupt */
|
||||
#define BRDY 0x0100 /* b8: Buffer ready interrupt */
|
||||
#define VBSTS 0x0080 /* b7: VBUS input port */
|
||||
#define DVSQ 0x0070 /* b6-4: Device state */
|
||||
#define DS_SPD_CNFG 0x0070 /* Suspend Configured */
|
||||
#define DS_SPD_ADDR 0x0060 /* Suspend Address */
|
||||
#define DS_SPD_DFLT 0x0050 /* Suspend Default */
|
||||
#define DS_SPD_POWR 0x0040 /* Suspend Powered */
|
||||
#define DS_SUSP 0x0040 /* Suspend */
|
||||
#define DS_CNFG 0x0030 /* Configured */
|
||||
#define DS_ADDS 0x0020 /* Address */
|
||||
#define DS_DFLT 0x0010 /* Default */
|
||||
#define DS_POWR 0x0000 /* Powered */
|
||||
#define DVSQS 0x0030 /* b5-4: Device state */
|
||||
#define VALID 0x0008 /* b3: Setup packet detected flag */
|
||||
#define CTSQ 0x0007 /* b2-0: Control transfer stage */
|
||||
#define CS_SQER 0x0006 /* Sequence error */
|
||||
#define CS_WRND 0x0005 /* Control write nodata status stage */
|
||||
#define CS_WRSS 0x0004 /* Control write status stage */
|
||||
#define CS_WRDS 0x0003 /* Control write data stage */
|
||||
#define CS_RDSS 0x0002 /* Control read status stage */
|
||||
#define CS_RDDS 0x0001 /* Control read data stage */
|
||||
#define CS_IDST 0x0000 /* Idle or setup stage */
|
||||
|
||||
/* Interrupt Status Register 1 */
|
||||
#define OVRCR 0x8000 /* b15: Over-current interrupt */
|
||||
#define BCHG 0x4000 /* b14: USB bus chenge interrupt */
|
||||
#define DTCH 0x1000 /* b12: Detach sense interrupt */
|
||||
#define ATTCH 0x0800 /* b11: Attach sense interrupt */
|
||||
#define EOFERR 0x0040 /* b6: EOF-error interrupt */
|
||||
#define SIGN 0x0020 /* b5: Setup ignore interrupt */
|
||||
#define SACK 0x0010 /* b4: Setup acknowledge interrupt */
|
||||
|
||||
/* Frame Number Register */
|
||||
#define OVRN 0x8000 /* b15: Overrun error */
|
||||
#define CRCE 0x4000 /* b14: Received data error */
|
||||
#define FRNM 0x07FF /* b10-0: Frame number */
|
||||
|
||||
/* Micro Frame Number Register */
|
||||
#define UFRNM 0x0007 /* b2-0: Micro frame number */
|
||||
|
||||
/* Default Control Pipe Maxpacket Size Register */
|
||||
/* Pipe Maxpacket Size Register */
|
||||
#define DEVSEL 0xF000 /* b15-14: Device address select */
|
||||
#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
|
||||
|
||||
/* Default Control Pipe Control Register */
|
||||
#define BSTS 0x8000 /* b15: Buffer status */
|
||||
#define SUREQ 0x4000 /* b14: Send USB request */
|
||||
#define CSCLR 0x2000 /* b13: complete-split status clear */
|
||||
#define CSSTS 0x1000 /* b12: complete-split status */
|
||||
#define SUREQCLR 0x0800 /* b11: stop setup request */
|
||||
#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
|
||||
#define SQSET 0x0080 /* b7: Sequence toggle bit set */
|
||||
#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
|
||||
#define PBUSY 0x0020 /* b5: pipe busy */
|
||||
#define PINGE 0x0010 /* b4: ping enable */
|
||||
#define CCPL 0x0004 /* b2: Enable control transfer complete */
|
||||
#define PID 0x0003 /* b1-0: Response PID */
|
||||
#define PID_STALL11 0x0003 /* STALL */
|
||||
#define PID_STALL 0x0002 /* STALL */
|
||||
#define PID_BUF 0x0001 /* BUF */
|
||||
#define PID_NAK 0x0000 /* NAK */
|
||||
|
||||
/* Pipe Window Select Register */
|
||||
#define PIPENM 0x0007 /* b2-0: Pipe select */
|
||||
|
||||
/* Pipe Configuration Register */
|
||||
#define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
|
||||
#define R8A66597_ISO 0xC000 /* Isochronous */
|
||||
#define R8A66597_INT 0x8000 /* Interrupt */
|
||||
#define R8A66597_BULK 0x4000 /* Bulk */
|
||||
#define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
|
||||
#define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
|
||||
#define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
|
||||
#define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
|
||||
#define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
|
||||
#define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
|
||||
|
||||
/* Pipe Buffer Configuration Register */
|
||||
#define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
|
||||
#define BUFNMB 0x007F /* b6-0: Pipe buffer number */
|
||||
#define PIPE0BUF 256
|
||||
#define PIPExBUF 64
|
||||
|
||||
/* Pipe Maxpacket Size Register */
|
||||
#define MXPS 0x07FF /* b10-0: Maxpacket size */
|
||||
|
||||
/* Pipe Cycle Configuration Register */
|
||||
#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
|
||||
#define IITV 0x0007 /* b2-0: Isochronous interval */
|
||||
|
||||
/* Pipex Control Register */
|
||||
#define BSTS 0x8000 /* b15: Buffer status */
|
||||
#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
|
||||
#define CSCLR 0x2000 /* b13: complete-split status clear */
|
||||
#define CSSTS 0x1000 /* b12: complete-split status */
|
||||
#define ATREPM 0x0400 /* b10: Auto repeat mode */
|
||||
#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
|
||||
#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
|
||||
#define SQSET 0x0080 /* b7: Sequence toggle bit set */
|
||||
#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
|
||||
#define PBUSY 0x0020 /* b5: pipe busy */
|
||||
#define PID 0x0003 /* b1-0: Response PID */
|
||||
|
||||
/* PIPExTRE */
|
||||
#define TRENB 0x0200 /* b9: Transaction counter enable */
|
||||
#define TRCLR 0x0100 /* b8: Transaction counter clear */
|
||||
|
||||
/* PIPExTRN */
|
||||
#define TRNCNT 0xFFFF /* b15-0: Transaction counter */
|
||||
|
||||
/* DEVADDx */
|
||||
#define UPPHUB 0x7800
|
||||
#define HUBPORT 0x0700
|
||||
#define USBSPD 0x00C0
|
||||
#define RTPORT 0x0001
|
||||
|
||||
#endif /* __LINUX_USB_R8A66597_H */
|
||||
|
||||
|
||||
@@ -59,6 +59,7 @@ enum port_dev_state {
|
||||
* @bulk_out_buffer: pointer to the bulk out buffer for this port.
|
||||
* @bulk_out_size: the size of the bulk_out_buffer, in bytes.
|
||||
* @write_urb: pointer to the bulk out struct urb for this port.
|
||||
* @write_fifo: kfifo used to buffer outgoing data
|
||||
* @write_urb_busy: port`s writing status
|
||||
* @bulk_out_endpointAddress: endpoint address for the bulk out pipe for this
|
||||
* port.
|
||||
@@ -96,6 +97,7 @@ struct usb_serial_port {
|
||||
unsigned char *bulk_out_buffer;
|
||||
int bulk_out_size;
|
||||
struct urb *write_urb;
|
||||
struct kfifo *write_fifo;
|
||||
int write_urb_busy;
|
||||
__u8 bulk_out_endpointAddress;
|
||||
|
||||
@@ -238,9 +240,8 @@ struct usb_serial_driver {
|
||||
int (*resume)(struct usb_serial *serial);
|
||||
|
||||
/* serial function calls */
|
||||
/* Called by console with tty = NULL and by tty */
|
||||
int (*open)(struct tty_struct *tty,
|
||||
struct usb_serial_port *port, struct file *filp);
|
||||
/* Called by console and by the tty layer */
|
||||
int (*open)(struct tty_struct *tty, struct usb_serial_port *port);
|
||||
void (*close)(struct usb_serial_port *port);
|
||||
int (*write)(struct tty_struct *tty, struct usb_serial_port *port,
|
||||
const unsigned char *buf, int count);
|
||||
@@ -261,6 +262,9 @@ struct usb_serial_driver {
|
||||
be an attached tty at this point */
|
||||
void (*dtr_rts)(struct usb_serial_port *port, int on);
|
||||
int (*carrier_raised)(struct usb_serial_port *port);
|
||||
/* Called by the usb serial hooks to allow the user to rework the
|
||||
termios state */
|
||||
void (*init_termios)(struct tty_struct *tty);
|
||||
/* USB events */
|
||||
void (*read_int_callback)(struct urb *urb);
|
||||
void (*write_int_callback)(struct urb *urb);
|
||||
@@ -300,7 +304,7 @@ static inline void usb_serial_console_disconnect(struct usb_serial *serial) {}
|
||||
extern struct usb_serial *usb_serial_get_by_index(unsigned int minor);
|
||||
extern void usb_serial_put(struct usb_serial *serial);
|
||||
extern int usb_serial_generic_open(struct tty_struct *tty,
|
||||
struct usb_serial_port *port, struct file *filp);
|
||||
struct usb_serial_port *port);
|
||||
extern int usb_serial_generic_write(struct tty_struct *tty,
|
||||
struct usb_serial_port *port, const unsigned char *buf, int count);
|
||||
extern void usb_serial_generic_close(struct usb_serial_port *port);
|
||||
|
||||
164
include/linux/usb/video.h
Normal file
164
include/linux/usb/video.h
Normal file
@@ -0,0 +1,164 @@
|
||||
/*
|
||||
* USB Video Class definitions.
|
||||
*
|
||||
* Copyright (C) 2009 Laurent Pinchart <laurent.pinchart@skynet.be>
|
||||
*
|
||||
* This file holds USB constants and structures defined by the USB Device
|
||||
* Class Definition for Video Devices. Unless otherwise stated, comments
|
||||
* below reference relevant sections of the USB Video Class 1.1 specification
|
||||
* available at
|
||||
*
|
||||
* http://www.usb.org/developers/devclass_docs/USB_Video_Class_1_1.zip
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_USB_VIDEO_H
|
||||
#define __LINUX_USB_VIDEO_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/* --------------------------------------------------------------------------
|
||||
* UVC constants
|
||||
*/
|
||||
|
||||
/* A.2. Video Interface Subclass Codes */
|
||||
#define UVC_SC_UNDEFINED 0x00
|
||||
#define UVC_SC_VIDEOCONTROL 0x01
|
||||
#define UVC_SC_VIDEOSTREAMING 0x02
|
||||
#define UVC_SC_VIDEO_INTERFACE_COLLECTION 0x03
|
||||
|
||||
/* A.3. Video Interface Protocol Codes */
|
||||
#define UVC_PC_PROTOCOL_UNDEFINED 0x00
|
||||
|
||||
/* A.5. Video Class-Specific VC Interface Descriptor Subtypes */
|
||||
#define UVC_VC_DESCRIPTOR_UNDEFINED 0x00
|
||||
#define UVC_VC_HEADER 0x01
|
||||
#define UVC_VC_INPUT_TERMINAL 0x02
|
||||
#define UVC_VC_OUTPUT_TERMINAL 0x03
|
||||
#define UVC_VC_SELECTOR_UNIT 0x04
|
||||
#define UVC_VC_PROCESSING_UNIT 0x05
|
||||
#define UVC_VC_EXTENSION_UNIT 0x06
|
||||
|
||||
/* A.6. Video Class-Specific VS Interface Descriptor Subtypes */
|
||||
#define UVC_VS_UNDEFINED 0x00
|
||||
#define UVC_VS_INPUT_HEADER 0x01
|
||||
#define UVC_VS_OUTPUT_HEADER 0x02
|
||||
#define UVC_VS_STILL_IMAGE_FRAME 0x03
|
||||
#define UVC_VS_FORMAT_UNCOMPRESSED 0x04
|
||||
#define UVC_VS_FRAME_UNCOMPRESSED 0x05
|
||||
#define UVC_VS_FORMAT_MJPEG 0x06
|
||||
#define UVC_VS_FRAME_MJPEG 0x07
|
||||
#define UVC_VS_FORMAT_MPEG2TS 0x0a
|
||||
#define UVC_VS_FORMAT_DV 0x0c
|
||||
#define UVC_VS_COLORFORMAT 0x0d
|
||||
#define UVC_VS_FORMAT_FRAME_BASED 0x10
|
||||
#define UVC_VS_FRAME_FRAME_BASED 0x11
|
||||
#define UVC_VS_FORMAT_STREAM_BASED 0x12
|
||||
|
||||
/* A.7. Video Class-Specific Endpoint Descriptor Subtypes */
|
||||
#define UVC_EP_UNDEFINED 0x00
|
||||
#define UVC_EP_GENERAL 0x01
|
||||
#define UVC_EP_ENDPOINT 0x02
|
||||
#define UVC_EP_INTERRUPT 0x03
|
||||
|
||||
/* A.8. Video Class-Specific Request Codes */
|
||||
#define UVC_RC_UNDEFINED 0x00
|
||||
#define UVC_SET_CUR 0x01
|
||||
#define UVC_GET_CUR 0x81
|
||||
#define UVC_GET_MIN 0x82
|
||||
#define UVC_GET_MAX 0x83
|
||||
#define UVC_GET_RES 0x84
|
||||
#define UVC_GET_LEN 0x85
|
||||
#define UVC_GET_INFO 0x86
|
||||
#define UVC_GET_DEF 0x87
|
||||
|
||||
/* A.9.1. VideoControl Interface Control Selectors */
|
||||
#define UVC_VC_CONTROL_UNDEFINED 0x00
|
||||
#define UVC_VC_VIDEO_POWER_MODE_CONTROL 0x01
|
||||
#define UVC_VC_REQUEST_ERROR_CODE_CONTROL 0x02
|
||||
|
||||
/* A.9.2. Terminal Control Selectors */
|
||||
#define UVC_TE_CONTROL_UNDEFINED 0x00
|
||||
|
||||
/* A.9.3. Selector Unit Control Selectors */
|
||||
#define UVC_SU_CONTROL_UNDEFINED 0x00
|
||||
#define UVC_SU_INPUT_SELECT_CONTROL 0x01
|
||||
|
||||
/* A.9.4. Camera Terminal Control Selectors */
|
||||
#define UVC_CT_CONTROL_UNDEFINED 0x00
|
||||
#define UVC_CT_SCANNING_MODE_CONTROL 0x01
|
||||
#define UVC_CT_AE_MODE_CONTROL 0x02
|
||||
#define UVC_CT_AE_PRIORITY_CONTROL 0x03
|
||||
#define UVC_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x04
|
||||
#define UVC_CT_EXPOSURE_TIME_RELATIVE_CONTROL 0x05
|
||||
#define UVC_CT_FOCUS_ABSOLUTE_CONTROL 0x06
|
||||
#define UVC_CT_FOCUS_RELATIVE_CONTROL 0x07
|
||||
#define UVC_CT_FOCUS_AUTO_CONTROL 0x08
|
||||
#define UVC_CT_IRIS_ABSOLUTE_CONTROL 0x09
|
||||
#define UVC_CT_IRIS_RELATIVE_CONTROL 0x0a
|
||||
#define UVC_CT_ZOOM_ABSOLUTE_CONTROL 0x0b
|
||||
#define UVC_CT_ZOOM_RELATIVE_CONTROL 0x0c
|
||||
#define UVC_CT_PANTILT_ABSOLUTE_CONTROL 0x0d
|
||||
#define UVC_CT_PANTILT_RELATIVE_CONTROL 0x0e
|
||||
#define UVC_CT_ROLL_ABSOLUTE_CONTROL 0x0f
|
||||
#define UVC_CT_ROLL_RELATIVE_CONTROL 0x10
|
||||
#define UVC_CT_PRIVACY_CONTROL 0x11
|
||||
|
||||
/* A.9.5. Processing Unit Control Selectors */
|
||||
#define UVC_PU_CONTROL_UNDEFINED 0x00
|
||||
#define UVC_PU_BACKLIGHT_COMPENSATION_CONTROL 0x01
|
||||
#define UVC_PU_BRIGHTNESS_CONTROL 0x02
|
||||
#define UVC_PU_CONTRAST_CONTROL 0x03
|
||||
#define UVC_PU_GAIN_CONTROL 0x04
|
||||
#define UVC_PU_POWER_LINE_FREQUENCY_CONTROL 0x05
|
||||
#define UVC_PU_HUE_CONTROL 0x06
|
||||
#define UVC_PU_SATURATION_CONTROL 0x07
|
||||
#define UVC_PU_SHARPNESS_CONTROL 0x08
|
||||
#define UVC_PU_GAMMA_CONTROL 0x09
|
||||
#define UVC_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x0a
|
||||
#define UVC_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x0b
|
||||
#define UVC_PU_WHITE_BALANCE_COMPONENT_CONTROL 0x0c
|
||||
#define UVC_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL 0x0d
|
||||
#define UVC_PU_DIGITAL_MULTIPLIER_CONTROL 0x0e
|
||||
#define UVC_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL 0x0f
|
||||
#define UVC_PU_HUE_AUTO_CONTROL 0x10
|
||||
#define UVC_PU_ANALOG_VIDEO_STANDARD_CONTROL 0x11
|
||||
#define UVC_PU_ANALOG_LOCK_STATUS_CONTROL 0x12
|
||||
|
||||
/* A.9.7. VideoStreaming Interface Control Selectors */
|
||||
#define UVC_VS_CONTROL_UNDEFINED 0x00
|
||||
#define UVC_VS_PROBE_CONTROL 0x01
|
||||
#define UVC_VS_COMMIT_CONTROL 0x02
|
||||
#define UVC_VS_STILL_PROBE_CONTROL 0x03
|
||||
#define UVC_VS_STILL_COMMIT_CONTROL 0x04
|
||||
#define UVC_VS_STILL_IMAGE_TRIGGER_CONTROL 0x05
|
||||
#define UVC_VS_STREAM_ERROR_CODE_CONTROL 0x06
|
||||
#define UVC_VS_GENERATE_KEY_FRAME_CONTROL 0x07
|
||||
#define UVC_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x08
|
||||
#define UVC_VS_SYNC_DELAY_CONTROL 0x09
|
||||
|
||||
/* B.1. USB Terminal Types */
|
||||
#define UVC_TT_VENDOR_SPECIFIC 0x0100
|
||||
#define UVC_TT_STREAMING 0x0101
|
||||
|
||||
/* B.2. Input Terminal Types */
|
||||
#define UVC_ITT_VENDOR_SPECIFIC 0x0200
|
||||
#define UVC_ITT_CAMERA 0x0201
|
||||
#define UVC_ITT_MEDIA_TRANSPORT_INPUT 0x0202
|
||||
|
||||
/* B.3. Output Terminal Types */
|
||||
#define UVC_OTT_VENDOR_SPECIFIC 0x0300
|
||||
#define UVC_OTT_DISPLAY 0x0301
|
||||
#define UVC_OTT_MEDIA_TRANSPORT_OUTPUT 0x0302
|
||||
|
||||
/* B.4. External Terminal Types */
|
||||
#define UVC_EXTERNAL_VENDOR_SPECIFIC 0x0400
|
||||
#define UVC_COMPOSITE_CONNECTOR 0x0401
|
||||
#define UVC_SVIDEO_CONNECTOR 0x0402
|
||||
#define UVC_COMPONENT_CONNECTOR 0x0403
|
||||
|
||||
/* 2.4.2.2. Status Packet Type */
|
||||
#define UVC_STATUS_TYPE_CONTROL 1
|
||||
#define UVC_STATUS_TYPE_STREAMING 2
|
||||
|
||||
#endif /* __LINUX_USB_VIDEO_H */
|
||||
|
||||
Reference in New Issue
Block a user