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Merge branch 'x86/platform' into x86/headers, to apply dependent patches

Browse Source 
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Ingo Molnar
2016-07-14 13:01:15 +02:00
parent 92d21ac74a 05f310e26f
commit 8b3843996d
25 changed files with 955 additions and 143 deletions
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20
arch/x86/platform/atom/punit_atom_debug.c
View File

@@ -23,10 +23,9 @@
#include <linux/seq_file.h>
#include <linux/io.h>
#include <asm/cpu_device_id.h>
#include <asm/intel-family.h>
#include <asm/iosf_mbi.h>
/* Power gate status reg */
#define PWRGT_STATUS 0x61
/* Subsystem config/status Video processor */
#define VED_SS_PM0 0x32
/* Subsystem config/status ISP (Image Signal Processor) */
@@ -35,12 +34,16 @@
#define MIO_SS_PM 0x3B
/* Shift bits for getting status for video, isp and i/o */
#define SSS_SHIFT 24
/* Power gate status reg */
#define PWRGT_STATUS 0x61
/* Shift bits for getting status for graphics rendering */
#define RENDER_POS 0
/* Shift bits for getting status for media control */
#define MEDIA_POS 2
/* Shift bits for getting status for Valley View/Baytrail display */
#define VLV_DISPLAY_POS 6
/* Subsystem config/status display for Cherry Trail SOC */
#define CHT_DSP_SSS 0x36
/* Shift bits for getting status for display */
@@ -52,6 +55,14 @@ struct punit_device {
int sss_pos;
};
static const struct punit_device punit_device_tng[] = {
{ "DISPLAY", CHT_DSP_SSS, SSS_SHIFT },
{ "VED", VED_SS_PM0, SSS_SHIFT },
{ "ISP", ISP_SS_PM0, SSS_SHIFT },
{ "MIO", MIO_SS_PM, SSS_SHIFT },
{ NULL }
};
static const struct punit_device punit_device_byt[] = {
{ "GFX RENDER", PWRGT_STATUS, RENDER_POS },
{ "GFX MEDIA", PWRGT_STATUS, MEDIA_POS },
@@ -143,8 +154,9 @@ static void punit_dbgfs_unregister(void)
(kernel_ulong_t)&drv_data }
static const struct x86_cpu_id intel_punit_cpu_ids[] = {
ICPU(55, punit_device_byt), /* Valleyview, Bay Trail */
ICPU(76, punit_device_cht), /* Braswell, Cherry Trail */
ICPU(INTEL_FAM6_ATOM_SILVERMONT1, punit_device_byt),
ICPU(INTEL_FAM6_ATOM_MERRIFIELD1, punit_device_tng),
ICPU(INTEL_FAM6_ATOM_AIRMONT, punit_device_cht),
{}
};

2
arch/x86/platform/intel-mid/Makefile
View File

@@ -1,4 +1,4 @@
obj-$(CONFIG_X86_INTEL_MID) += intel-mid.o intel_mid_vrtc.o mfld.o mrfl.o
obj-$(CONFIG_X86_INTEL_MID) += intel-mid.o intel_mid_vrtc.o mfld.o mrfld.o pwr.o
# SFI specific code
ifdef CONFIG_X86_INTEL_MID

10
arch/x86/platform/intel-mid/device_libs/Makefile
View File

@@ -1,3 +1,5 @@
# Family-Level Interface Shim (FLIS)
obj-$(subst m,y,$(CONFIG_PINCTRL_MERRIFIELD)) += platform_mrfld_pinctrl.o
# IPC Devices
obj-y += platform_ipc.o
obj-$(subst m,y,$(CONFIG_MFD_INTEL_MSIC)) += platform_msic.o
@@ -8,14 +10,18 @@ obj-$(subst m,y,$(CONFIG_MFD_INTEL_MSIC)) += platform_msic_battery.o
obj-$(subst m,y,$(CONFIG_INTEL_MID_POWER_BUTTON)) += platform_msic_power_btn.o
obj-$(subst m,y,$(CONFIG_GPIO_INTEL_PMIC)) += platform_pmic_gpio.o
obj-$(subst m,y,$(CONFIG_INTEL_MFLD_THERMAL)) += platform_msic_thermal.o
# SPI Devices
obj-$(subst m,y,$(CONFIG_SPI_SPIDEV)) += platform_spidev.o
# I2C Devices
obj-$(subst m,y,$(CONFIG_SENSORS_EMC1403)) += platform_emc1403.o
obj-$(subst m,y,$(CONFIG_SENSORS_LIS3LV02D)) += platform_lis331.o
obj-$(subst m,y,$(CONFIG_GPIO_PCA953X)) += platform_max7315.o
obj-$(subst m,y,$(CONFIG_INPUT_MPU3050)) += platform_mpu3050.o
obj-$(subst m,y,$(CONFIG_INPUT_BMA150)) += platform_bma023.o
obj-$(subst m,y,$(CONFIG_GPIO_PCA953X)) += platform_tca6416.o
obj-$(subst m,y,$(CONFIG_DRM_MEDFIELD)) += platform_tc35876x.o
# I2C GPIO Expanders
obj-$(subst m,y,$(CONFIG_GPIO_PCA953X)) += platform_max7315.o
obj-$(subst m,y,$(CONFIG_GPIO_PCA953X)) += platform_pcal9555a.o
obj-$(subst m,y,$(CONFIG_GPIO_PCA953X)) += platform_tca6416.o
# MISC Devices
obj-$(subst m,y,$(CONFIG_KEYBOARD_GPIO)) += platform_gpio_keys.o
obj-$(subst m,y,$(CONFIG_INTEL_MID_WATCHDOG)) += platform_wdt.o

43
arch/x86/platform/intel-mid/device_libs/platform_mrfld_pinctrl.c Normal file
View File

@@ -0,0 +1,43 @@
/*
* Intel Merrifield FLIS platform device initialization file
*
* Copyright (C) 2016, Intel Corporation
*
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2
* of the License.
*/
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <asm/intel-mid.h>
#define FLIS_BASE_ADDR 0xff0c0000
#define FLIS_LENGTH 0x8000
static struct resource mrfld_pinctrl_mmio_resource = {
.start = FLIS_BASE_ADDR,
.end = FLIS_BASE_ADDR + FLIS_LENGTH - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device mrfld_pinctrl_device = {
.name = "pinctrl-merrifield",
.id = PLATFORM_DEVID_NONE,
.resource = &mrfld_pinctrl_mmio_resource,
.num_resources = 1,
};
static int __init mrfld_pinctrl_init(void)
{
if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
return platform_device_register(&mrfld_pinctrl_device);
return -ENODEV;
}
arch_initcall(mrfld_pinctrl_init);

99
arch/x86/platform/intel-mid/device_libs/platform_pcal9555a.c Normal file
View File

@@ -0,0 +1,99 @@
/*
* PCAL9555a platform data initilization file
*
* Copyright (C) 2016, Intel Corporation
*
* Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* Dan O'Donovan <dan@emutex.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2
* of the License.
*/
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/platform_data/pca953x.h>
#include <linux/sfi.h>
#include <asm/intel-mid.h>
#define PCAL9555A_NUM 4
static struct pca953x_platform_data pcal9555a_pdata[PCAL9555A_NUM];
static int nr;
static void __init *pcal9555a_platform_data(void *info)
{
struct i2c_board_info *i2c_info = info;
char *type = i2c_info->type;
struct pca953x_platform_data *pcal9555a;
char base_pin_name[SFI_NAME_LEN + 1];
char intr_pin_name[SFI_NAME_LEN + 1];
int gpio_base, intr;
snprintf(base_pin_name, sizeof(base_pin_name), "%s_base", type);
snprintf(intr_pin_name, sizeof(intr_pin_name), "%s_int", type);
gpio_base = get_gpio_by_name(base_pin_name);
intr = get_gpio_by_name(intr_pin_name);
/* Check if the SFI record valid */
if (gpio_base == -1)
return NULL;
if (nr >= PCAL9555A_NUM) {
pr_err("%s: Too many instances, only %d supported\n", __func__,
PCAL9555A_NUM);
return NULL;
}
pcal9555a = &pcal9555a_pdata[nr++];
pcal9555a->gpio_base = gpio_base;
if (intr >= 0) {
i2c_info->irq = intr + INTEL_MID_IRQ_OFFSET;
pcal9555a->irq_base = gpio_base + INTEL_MID_IRQ_OFFSET;
} else {
i2c_info->irq = -1;
pcal9555a->irq_base = -1;
}
strcpy(type, "pcal9555a");
return pcal9555a;
}
static const struct devs_id pcal9555a_1_dev_id __initconst = {
.name = "pcal9555a-1",
.type = SFI_DEV_TYPE_I2C,
.delay = 1,
.get_platform_data = &pcal9555a_platform_data,
};
static const struct devs_id pcal9555a_2_dev_id __initconst = {
.name = "pcal9555a-2",
.type = SFI_DEV_TYPE_I2C,
.delay = 1,
.get_platform_data = &pcal9555a_platform_data,
};
static const struct devs_id pcal9555a_3_dev_id __initconst = {
.name = "pcal9555a-3",
.type = SFI_DEV_TYPE_I2C,
.delay = 1,
.get_platform_data = &pcal9555a_platform_data,
};
static const struct devs_id pcal9555a_4_dev_id __initconst = {
.name = "pcal9555a-4",
.type = SFI_DEV_TYPE_I2C,
.delay = 1,
.get_platform_data = &pcal9555a_platform_data,
};
sfi_device(pcal9555a_1_dev_id);
sfi_device(pcal9555a_2_dev_id);
sfi_device(pcal9555a_3_dev_id);
sfi_device(pcal9555a_4_dev_id);

50
arch/x86/platform/intel-mid/device_libs/platform_spidev.c Normal file
View File

@@ -0,0 +1,50 @@
/*
* spidev platform data initilization file
*
* (C) Copyright 2014, 2016 Intel Corporation
* Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* Dan O'Donovan <dan@emutex.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2
* of the License.
*/
#include <linux/init.h>
#include <linux/sfi.h>
#include <linux/spi/pxa2xx_spi.h>
#include <linux/spi/spi.h>
#include <asm/intel-mid.h>
#define MRFLD_SPI_DEFAULT_DMA_BURST 8
#define MRFLD_SPI_DEFAULT_TIMEOUT 500
/* GPIO pin for spidev chipselect */
#define MRFLD_SPIDEV_GPIO_CS 111
static struct pxa2xx_spi_chip spidev_spi_chip = {
.dma_burst_size = MRFLD_SPI_DEFAULT_DMA_BURST,
.timeout = MRFLD_SPI_DEFAULT_TIMEOUT,
.gpio_cs = MRFLD_SPIDEV_GPIO_CS,
};
static void __init *spidev_platform_data(void *info)
{
struct spi_board_info *spi_info = info;
spi_info->mode = SPI_MODE_0;
spi_info->controller_data = &spidev_spi_chip;
return NULL;
}
static const struct devs_id spidev_dev_id __initconst = {
.name = "spidev",
.type = SFI_DEV_TYPE_SPI,
.delay = 0,
.get_platform_data = &spidev_platform_data,
};
sfi_device(spidev_dev_id);

10
arch/x86/platform/intel-mid/intel-mid.c
View File

@@ -16,6 +16,7 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/regulator/machine.h>
#include <linux/scatterlist.h>
#include <linux/sfi.h>
#include <linux/irq.h>
@@ -144,6 +145,15 @@ static void intel_mid_arch_setup(void)
out:
if (intel_mid_ops->arch_setup)
intel_mid_ops->arch_setup();
/*
* Intel MID platforms are using explicitly defined regulators.
*
* Let the regulator core know that we do not have any additional
* regulators left. This lets it substitute unprovided regulators with
* dummy ones:
*/
regulator_has_full_constraints();
}
/* MID systems don't have i8042 controller */

2
arch/x86/platform/intel-mid/mrfl.c → arch/x86/platform/intel-mid/mrfld.c
View File

@@ -1,5 +1,5 @@
/*
* mrfl.c: Intel Merrifield platform specific setup code
* Intel Merrifield platform specific setup code
*
* (C) Copyright 2013 Intel Corporation
*

418
arch/x86/platform/intel-mid/pwr.c Normal file
View File

@@ -0,0 +1,418 @@
/*
* Intel MID Power Management Unit (PWRMU) device driver
*
* Copyright (C) 2016, Intel Corporation
*
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* Intel MID Power Management Unit device driver handles the South Complex PCI
* devices such as GPDMA, SPI, I2C, PWM, and so on. By default PCI core
* modifies bits in PMCSR register in the PCI configuration space. This is not
* enough on some SoCs like Intel Tangier. In such case PCI core sets a new
* power state of the device in question through a PM hook registered in struct
* pci_platform_pm_ops (see drivers/pci/pci-mid.c).
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/pci.h>
#include <asm/intel-mid.h>
/* Registers */
#define PM_STS 0x00
#define PM_CMD 0x04
#define PM_ICS 0x08
#define PM_WKC(x) (0x10 + (x) * 4)
#define PM_WKS(x) (0x18 + (x) * 4)
#define PM_SSC(x) (0x20 + (x) * 4)
#define PM_SSS(x) (0x30 + (x) * 4)
/* Bits in PM_STS */
#define PM_STS_BUSY (1 << 8)
/* Bits in PM_CMD */
#define PM_CMD_CMD(x) ((x) << 0)
#define PM_CMD_IOC (1 << 8)
#define PM_CMD_D3cold (1 << 21)
/* List of commands */
#define CMD_SET_CFG 0x01
/* Bits in PM_ICS */
#define PM_ICS_INT_STATUS(x) ((x) & 0xff)
#define PM_ICS_IE (1 << 8)
#define PM_ICS_IP (1 << 9)
#define PM_ICS_SW_INT_STS (1 << 10)
/* List of interrupts */
#define INT_INVALID 0
#define INT_CMD_COMPLETE 1
#define INT_CMD_ERR 2
#define INT_WAKE_EVENT 3
#define INT_LSS_POWER_ERR 4
#define INT_S0iX_MSG_ERR 5
#define INT_NO_C6 6
#define INT_TRIGGER_ERR 7
#define INT_INACTIVITY 8
/* South Complex devices */
#define LSS_MAX_SHARED_DEVS 4
#define LSS_MAX_DEVS 64
#define LSS_WS_BITS 1 /* wake state width */
#define LSS_PWS_BITS 2 /* power state width */
/* Supported device IDs */
#define PCI_DEVICE_ID_PENWELL 0x0828
#define PCI_DEVICE_ID_TANGIER 0x11a1
struct mid_pwr_dev {
struct pci_dev *pdev;
pci_power_t state;
};
struct mid_pwr {
struct device *dev;
void __iomem *regs;
int irq;
bool available;
struct mutex lock;
struct mid_pwr_dev lss[LSS_MAX_DEVS][LSS_MAX_SHARED_DEVS];
};
static struct mid_pwr *midpwr;
static u32 mid_pwr_get_state(struct mid_pwr *pwr, int reg)
{
return readl(pwr->regs + PM_SSS(reg));
}
static void mid_pwr_set_state(struct mid_pwr *pwr, int reg, u32 value)
{
writel(value, pwr->regs + PM_SSC(reg));
}
static void mid_pwr_set_wake(struct mid_pwr *pwr, int reg, u32 value)
{
writel(value, pwr->regs + PM_WKC(reg));
}
static void mid_pwr_interrupt_disable(struct mid_pwr *pwr)
{
writel(~PM_ICS_IE, pwr->regs + PM_ICS);
}
static bool mid_pwr_is_busy(struct mid_pwr *pwr)
{
return !!(readl(pwr->regs + PM_STS) & PM_STS_BUSY);
}
/* Wait 500ms that the latest PWRMU command finished */
static int mid_pwr_wait(struct mid_pwr *pwr)
{
unsigned int count = 500000;
bool busy;
do {
busy = mid_pwr_is_busy(pwr);
if (!busy)
return 0;
udelay(1);
} while (--count);
return -EBUSY;
}
static int mid_pwr_wait_for_cmd(struct mid_pwr *pwr, u8 cmd)
{
writel(PM_CMD_CMD(cmd), pwr->regs + PM_CMD);
return mid_pwr_wait(pwr);
}
static int __update_power_state(struct mid_pwr *pwr, int reg, int bit, int new)
{
int curstate;
u32 power;
int ret;
/* Check if the device is already in desired state */
power = mid_pwr_get_state(pwr, reg);
curstate = (power >> bit) & 3;
if (curstate == new)
return 0;
/* Update the power state */
mid_pwr_set_state(pwr, reg, (power & ~(3 << bit)) | (new << bit));
/* Send command to SCU */
ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG);
if (ret)
return ret;
/* Check if the device is already in desired state */
power = mid_pwr_get_state(pwr, reg);
curstate = (power >> bit) & 3;
if (curstate != new)
return -EAGAIN;
return 0;
}
static pci_power_t __find_weakest_power_state(struct mid_pwr_dev *lss,
struct pci_dev *pdev,
pci_power_t state)
{
pci_power_t weakest = PCI_D3hot;
unsigned int j;
/* Find device in cache or first free cell */
for (j = 0; j < LSS_MAX_SHARED_DEVS; j++) {
if (lss[j].pdev == pdev || !lss[j].pdev)
break;
}
/* Store the desired state in cache */
if (j < LSS_MAX_SHARED_DEVS) {
lss[j].pdev = pdev;
lss[j].state = state;
} else {
dev_WARN(&pdev->dev, "No room for device in PWRMU LSS cache\n");
weakest = state;
}
/* Find the power state we may use */
for (j = 0; j < LSS_MAX_SHARED_DEVS; j++) {
if (lss[j].state < weakest)
weakest = lss[j].state;
}
return weakest;
}
static int __set_power_state(struct mid_pwr *pwr, struct pci_dev *pdev,
pci_power_t state, int id, int reg, int bit)
{
const char *name;
int ret;
state = __find_weakest_power_state(pwr->lss[id], pdev, state);
name = pci_power_name(state);
ret = __update_power_state(pwr, reg, bit, (__force int)state);
if (ret) {
dev_warn(&pdev->dev, "Can't set power state %s: %d\n", name, ret);
return ret;
}
dev_vdbg(&pdev->dev, "Set power state %s\n", name);
return 0;
}
static int mid_pwr_set_power_state(struct mid_pwr *pwr, struct pci_dev *pdev,
pci_power_t state)
{
int id, reg, bit;
int ret;
id = intel_mid_pwr_get_lss_id(pdev);
if (id < 0)
return id;
reg = (id * LSS_PWS_BITS) / 32;
bit = (id * LSS_PWS_BITS) % 32;
/* We support states between PCI_D0 and PCI_D3hot */
if (state < PCI_D0)
state = PCI_D0;
if (state > PCI_D3hot)
state = PCI_D3hot;
mutex_lock(&pwr->lock);
ret = __set_power_state(pwr, pdev, state, id, reg, bit);
mutex_unlock(&pwr->lock);
return ret;
}
int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
{
struct mid_pwr *pwr = midpwr;
int ret = 0;
might_sleep();
if (pwr && pwr->available)
ret = mid_pwr_set_power_state(pwr, pdev, state);
dev_vdbg(&pdev->dev, "set_power_state() returns %d\n", ret);
return 0;
}
EXPORT_SYMBOL_GPL(intel_mid_pci_set_power_state);
int intel_mid_pwr_get_lss_id(struct pci_dev *pdev)
{
int vndr;
u8 id;
/*
* Mapping to PWRMU index is kept in the Logical SubSystem ID byte of
* Vendor capability.
*/
vndr = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
if (!vndr)
return -EINVAL;
/* Read the Logical SubSystem ID byte */
pci_read_config_byte(pdev, vndr + INTEL_MID_PWR_LSS_OFFSET, &id);
if (!(id & INTEL_MID_PWR_LSS_TYPE))
return -ENODEV;
id &= ~INTEL_MID_PWR_LSS_TYPE;
if (id >= LSS_MAX_DEVS)
return -ERANGE;
return id;
}
static irqreturn_t mid_pwr_irq_handler(int irq, void *dev_id)
{
struct mid_pwr *pwr = dev_id;
u32 ics;
ics = readl(pwr->regs + PM_ICS);
if (!(ics & PM_ICS_IP))
return IRQ_NONE;
writel(ics | PM_ICS_IP, pwr->regs + PM_ICS);
dev_warn(pwr->dev, "Unexpected IRQ: %#x\n", PM_ICS_INT_STATUS(ics));
return IRQ_HANDLED;
}
struct mid_pwr_device_info {
int (*set_initial_state)(struct mid_pwr *pwr);
};
static int mid_pwr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct mid_pwr_device_info *info = (void *)id->driver_data;
struct device *dev = &pdev->dev;
struct mid_pwr *pwr;
int ret;
ret = pcim_enable_device(pdev);
if (ret < 0) {
dev_err(&pdev->dev, "error: could not enable device\n");
return ret;
}
ret = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
if (ret) {
dev_err(&pdev->dev, "I/O memory remapping failed\n");
return ret;
}
pwr = devm_kzalloc(dev, sizeof(*pwr), GFP_KERNEL);
if (!pwr)
return -ENOMEM;
pwr->dev = dev;
pwr->regs = pcim_iomap_table(pdev)[0];
pwr->irq = pdev->irq;
mutex_init(&pwr->lock);
/* Disable interrupts */
mid_pwr_interrupt_disable(pwr);
if (info && info->set_initial_state) {
ret = info->set_initial_state(pwr);
if (ret)
dev_warn(dev, "Can't set initial state: %d\n", ret);
}
ret = devm_request_irq(dev, pdev->irq, mid_pwr_irq_handler,
IRQF_NO_SUSPEND, pci_name(pdev), pwr);
if (ret)
return ret;
pwr->available = true;
midpwr = pwr;
pci_set_drvdata(pdev, pwr);
return 0;
}
static int mid_set_initial_state(struct mid_pwr *pwr)
{
unsigned int i, j;
int ret;
/*
* Enable wake events.
*
* PWRMU supports up to 32 sources for wake up the system. Ungate them
* all here.
*/
mid_pwr_set_wake(pwr, 0, 0xffffffff);
mid_pwr_set_wake(pwr, 1, 0xffffffff);
/*
* Power off South Complex devices.
*
* There is a map (see a note below) of 64 devices with 2 bits per each
* on 32-bit HW registers. The following calls set all devices to one
* known initial state, i.e. PCI_D3hot. This is done in conjunction
* with PMCSR setting in arch/x86/pci/intel_mid_pci.c.
*
* NOTE: The actual device mapping is provided by a platform at run
* time using vendor capability of PCI configuration space.
*/
mid_pwr_set_state(pwr, 0, 0xffffffff);
mid_pwr_set_state(pwr, 1, 0xffffffff);
mid_pwr_set_state(pwr, 2, 0xffffffff);
mid_pwr_set_state(pwr, 3, 0xffffffff);
/* Send command to SCU */
ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG);
if (ret)
return ret;
for (i = 0; i < LSS_MAX_DEVS; i++) {
for (j = 0; j < LSS_MAX_SHARED_DEVS; j++)
pwr->lss[i][j].state = PCI_D3hot;
}
return 0;
}
static const struct mid_pwr_device_info mid_info = {
.set_initial_state = mid_set_initial_state,
};
static const struct pci_device_id mid_pwr_pci_ids[] = {
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&mid_info },
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&mid_info },
{}
};
MODULE_DEVICE_TABLE(pci, mid_pwr_pci_ids);
static struct pci_driver mid_pwr_pci_driver = {
.name = "intel_mid_pwr",
.probe = mid_pwr_probe,
.id_table = mid_pwr_pci_ids,
};
builtin_pci_driver(mid_pwr_pci_driver);

29
arch/x86/platform/intel-mid/sfi.c
View File

@@ -407,6 +407,32 @@ static void __init sfi_handle_i2c_dev(struct sfi_device_table_entry *pentry,
i2c_register_board_info(pentry->host_num, &i2c_info, 1);
}
static void __init sfi_handle_sd_dev(struct sfi_device_table_entry *pentry,
struct devs_id *dev)
{
struct mid_sd_board_info sd_info;
void *pdata;
memset(&sd_info, 0, sizeof(sd_info));
strncpy(sd_info.name, pentry->name, SFI_NAME_LEN);
sd_info.bus_num = pentry->host_num;
sd_info.max_clk = pentry->max_freq;
sd_info.addr = pentry->addr;
pr_debug("SD bus = %d, name = %16.16s, max_clk = %d, addr = 0x%x\n",
sd_info.bus_num,
sd_info.name,
sd_info.max_clk,
sd_info.addr);
pdata = intel_mid_sfi_get_pdata(dev, &sd_info);
if (IS_ERR(pdata))
return;
/* Nothing we can do with this for now */
sd_info.platform_data = pdata;
pr_debug("Successfully registered %16.16s", sd_info.name);
}
extern struct devs_id *const __x86_intel_mid_dev_start[],
*const __x86_intel_mid_dev_end[];
@@ -490,6 +516,9 @@ static int __init sfi_parse_devs(struct sfi_table_header *table)
case SFI_DEV_TYPE_I2C:
sfi_handle_i2c_dev(pentry, dev);
break;
case SFI_DEV_TYPE_SD:
sfi_handle_sd_dev(pentry, dev);
break;
case SFI_DEV_TYPE_UART:
case SFI_DEV_TYPE_HSI:
default: