[SPARC64]: More TLB/TSB handling fixes.
The SUN4V convention with non-shared TSBs is that the context bit of the TAG is clear. So we have to choose an "invalid" bit and initialize new TSBs appropriately. Otherwise a zero TAG looks "valid". Make sure, for the window fixup cases, that we use the right global registers and that we don't potentially trample on the live global registers in etrap/rtrap handling (%g2 and %g6) and that we put the missing virtual address properly in %g5. Signed-off-by: David S. Miller <davem@davemloft.net>
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@@ -36,7 +36,7 @@ tsb_miss_itlb:
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/* At this point we have:
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* %g4 -- missing virtual address
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* %g1 -- TSB entry address
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* %g6 -- TAG TARGET ((vaddr >> 22) | (ctx << 48))
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* %g6 -- TAG TARGET (vaddr >> 22)
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*/
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tsb_miss_page_table_walk:
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TRAP_LOAD_PGD_PHYS(%g7, %g5)
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@@ -50,8 +50,10 @@ tsb_reload:
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/* Load and check PTE. */
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ldxa [%g5] ASI_PHYS_USE_EC, %g5
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mov 1, %g7
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sllx %g7, TSB_TAG_INVALID_BIT, %g7
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brgez,a,pn %g5, tsb_do_fault
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TSB_STORE(%g1, %g0)
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TSB_STORE(%g1, %g7)
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/* If it is larger than the base page size, don't
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* bother putting it into the TSB.
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@@ -62,8 +64,10 @@ tsb_reload:
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sethi %hi(_PAGE_SZBITS), %g7
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ldx [%g7 + %lo(_PAGE_SZBITS)], %g7
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cmp %g2, %g7
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mov 1, %g7
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sllx %g7, TSB_TAG_INVALID_BIT, %g7
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bne,a,pn %xcc, tsb_tlb_reload
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TSB_STORE(%g1, %g0)
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TSB_STORE(%g1, %g7)
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TSB_WRITE(%g1, %g5, %g6)
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@@ -136,7 +140,7 @@ tsb_do_fault:
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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SET_GL(1)
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ldxa [%g0] ASI_SCRATCHPAD, %g2
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ldxa [%g0] ASI_SCRATCHPAD, %g4
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.previous
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bne,pn %xcc, tsb_do_itlb_fault
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@@ -150,7 +154,7 @@ tsb_do_dtlb_fault:
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ldxa [%g4] ASI_DMMU, %g5
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g5
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ldx [%g4 + HV_FAULT_D_ADDR_OFFSET], %g5
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nop
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.previous
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@@ -217,8 +221,9 @@ tsb_flush:
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bne,pn %icc, 1b
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membar #LoadLoad
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cmp %g1, %o1
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mov 1, %o3
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bne,pt %xcc, 2f
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clr %o3
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sllx %o3, TSB_TAG_INVALID_BIT, %o3
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TSB_CAS_TAG(%o0, %g1, %o3)
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cmp %g1, %o3
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bne,pn %xcc, 1b
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