Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1745 commits) dp83640: free packet queues on remove dp83640: use proper function to free transmit time stamping packets ipv6: Do not use routes from locally generated RAs |PATCH net-next] tg3: add tx_dropped counter be2net: don't create multiple RX/TX rings in multi channel mode be2net: don't create multiple TXQs in BE2 be2net: refactor VF setup/teardown code into be_vf_setup/clear() be2net: add vlan/rx-mode/flow-control config to be_setup() net_sched: cls_flow: use skb_header_pointer() ipv4: avoid useless call of the function check_peer_pmtu TCP: remove TCP_DEBUG net: Fix driver name for mdio-gpio.c ipv4: tcp: fix TOS value in ACK messages sent from TIME_WAIT rtnetlink: Add missing manual netlink notification in dev_change_net_namespaces ipv4: fix ipsec forward performance regression jme: fix irq storm after suspend/resume route: fix ICMP redirect validation net: hold sock reference while processing tx timestamps tcp: md5: add more const attributes Add ethtool -g support to virtio_net ... Fix up conflicts in: - drivers/net/Kconfig: The split-up generated a trivial conflict with removal of a stale reference to Documentation/networking/net-modules.txt. Remove it from the new location instead. - fs/sysfs/dir.c: Fairly nasty conflicts with the sysfs rb-tree usage, conflicting with Eric Biederman's changes for tagged directories.
This commit is contained in:
Linus Torvalds
3
drivers/net/ethernet/atheros/atlx/Makefile
Normal file
3
drivers/net/ethernet/atheros/atlx/Makefile
Normal file
@@ -0,0 +1,3 @@
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||||
obj-$(CONFIG_ATL1) += atl1.o
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obj-$(CONFIG_ATL2) += atl2.o
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||||
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3668
drivers/net/ethernet/atheros/atlx/atl1.c
Normal file
3668
drivers/net/ethernet/atheros/atlx/atl1.c
Normal file
File diff suppressed because it is too large
Load Diff
792
drivers/net/ethernet/atheros/atlx/atl1.h
Normal file
792
drivers/net/ethernet/atheros/atlx/atl1.h
Normal file
@@ -0,0 +1,792 @@
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/*
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* Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
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* Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
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* Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
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*
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* Derived from Intel e1000 driver
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* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59
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||||
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef ATL1_H
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#define ATL1_H
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#include <linux/compiler.h>
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#include <linux/ethtool.h>
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#include <linux/if_vlan.h>
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#include <linux/mii.h>
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#include <linux/module.h>
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#include <linux/skbuff.h>
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#include <linux/spinlock.h>
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#include <linux/timer.h>
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#include <linux/types.h>
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#include <linux/workqueue.h>
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#include "atlx.h"
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#define ATLX_DRIVER_NAME "atl1"
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MODULE_DESCRIPTION("Atheros L1 Gigabit Ethernet Driver");
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#define atlx_adapter atl1_adapter
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#define atlx_check_for_link atl1_check_for_link
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#define atlx_check_link atl1_check_link
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#define atlx_hash_mc_addr atl1_hash_mc_addr
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#define atlx_hash_set atl1_hash_set
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#define atlx_hw atl1_hw
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#define atlx_mii_ioctl atl1_mii_ioctl
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#define atlx_read_phy_reg atl1_read_phy_reg
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#define atlx_set_mac atl1_set_mac
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#define atlx_set_mac_addr atl1_set_mac_addr
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struct atl1_adapter;
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struct atl1_hw;
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|
||||
/* function prototypes needed by multiple files */
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static u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr);
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static void atl1_hash_set(struct atl1_hw *hw, u32 hash_value);
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static void atl1_set_mac_addr(struct atl1_hw *hw);
|
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static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
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int cmd);
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static u32 atl1_check_link(struct atl1_adapter *adapter);
|
||||
|
||||
/* hardware definitions specific to L1 */
|
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|
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/* Block IDLE Status Register */
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#define IDLE_STATUS_RXMAC 0x1
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#define IDLE_STATUS_TXMAC 0x2
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#define IDLE_STATUS_RXQ 0x4
|
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#define IDLE_STATUS_TXQ 0x8
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#define IDLE_STATUS_DMAR 0x10
|
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#define IDLE_STATUS_DMAW 0x20
|
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#define IDLE_STATUS_SMB 0x40
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#define IDLE_STATUS_CMB 0x80
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|
||||
/* MDIO Control Register */
|
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#define MDIO_WAIT_TIMES 30
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|
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/* MAC Control Register */
|
||||
#define MAC_CTRL_TX_PAUSE 0x10000
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#define MAC_CTRL_SCNT 0x20000
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#define MAC_CTRL_SRST_TX 0x40000
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#define MAC_CTRL_TX_SIMURST 0x80000
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#define MAC_CTRL_SPEED_SHIFT 20
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#define MAC_CTRL_SPEED_MASK 0x300000
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||||
#define MAC_CTRL_SPEED_1000 0x2
|
||||
#define MAC_CTRL_SPEED_10_100 0x1
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#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000
|
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#define MAC_CTRL_TX_HUGE 0x800000
|
||||
#define MAC_CTRL_RX_CHKSUM_EN 0x1000000
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#define MAC_CTRL_DBG 0x8000000
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||||
|
||||
/* Wake-On-Lan control register */
|
||||
#define WOL_CLK_SWITCH_EN 0x8000
|
||||
#define WOL_PT5_EN 0x200000
|
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#define WOL_PT6_EN 0x400000
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#define WOL_PT5_MATCH 0x8000000
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#define WOL_PT6_MATCH 0x10000000
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||||
|
||||
/* WOL Length ( 2 DWORD ) */
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#define REG_WOL_PATTERN_LEN 0x14A4
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#define WOL_PT_LEN_MASK 0x7F
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#define WOL_PT0_LEN_SHIFT 0
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#define WOL_PT1_LEN_SHIFT 8
|
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#define WOL_PT2_LEN_SHIFT 16
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#define WOL_PT3_LEN_SHIFT 24
|
||||
#define WOL_PT4_LEN_SHIFT 0
|
||||
#define WOL_PT5_LEN_SHIFT 8
|
||||
#define WOL_PT6_LEN_SHIFT 16
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||||
|
||||
/* Internal SRAM Partition Registers, low 32 bits */
|
||||
#define REG_SRAM_RFD_LEN 0x1504
|
||||
#define REG_SRAM_RRD_ADDR 0x1508
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||||
#define REG_SRAM_RRD_LEN 0x150C
|
||||
#define REG_SRAM_TPD_ADDR 0x1510
|
||||
#define REG_SRAM_TPD_LEN 0x1514
|
||||
#define REG_SRAM_TRD_ADDR 0x1518
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#define REG_SRAM_TRD_LEN 0x151C
|
||||
#define REG_SRAM_RXF_ADDR 0x1520
|
||||
#define REG_SRAM_RXF_LEN 0x1524
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#define REG_SRAM_TXF_ADDR 0x1528
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#define REG_SRAM_TXF_LEN 0x152C
|
||||
#define REG_SRAM_TCPH_PATH_ADDR 0x1530
|
||||
#define SRAM_TCPH_ADDR_MASK 0xFFF
|
||||
#define SRAM_TCPH_ADDR_SHIFT 0
|
||||
#define SRAM_PATH_ADDR_MASK 0xFFF
|
||||
#define SRAM_PATH_ADDR_SHIFT 16
|
||||
|
||||
/* Load Ptr Register */
|
||||
#define REG_LOAD_PTR 0x1534
|
||||
|
||||
/* Descriptor Control registers, low 32 bits */
|
||||
#define REG_DESC_RFD_ADDR_LO 0x1544
|
||||
#define REG_DESC_RRD_ADDR_LO 0x1548
|
||||
#define REG_DESC_TPD_ADDR_LO 0x154C
|
||||
#define REG_DESC_CMB_ADDR_LO 0x1550
|
||||
#define REG_DESC_SMB_ADDR_LO 0x1554
|
||||
#define REG_DESC_RFD_RRD_RING_SIZE 0x1558
|
||||
#define DESC_RFD_RING_SIZE_MASK 0x7FF
|
||||
#define DESC_RFD_RING_SIZE_SHIFT 0
|
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#define DESC_RRD_RING_SIZE_MASK 0x7FF
|
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#define DESC_RRD_RING_SIZE_SHIFT 16
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||||
#define REG_DESC_TPD_RING_SIZE 0x155C
|
||||
#define DESC_TPD_RING_SIZE_MASK 0x3FF
|
||||
#define DESC_TPD_RING_SIZE_SHIFT 0
|
||||
|
||||
/* TXQ Control Register */
|
||||
#define REG_TXQ_CTRL 0x1580
|
||||
#define TXQ_CTRL_TPD_BURST_NUM_SHIFT 0
|
||||
#define TXQ_CTRL_TPD_BURST_NUM_MASK 0x1F
|
||||
#define TXQ_CTRL_EN 0x20
|
||||
#define TXQ_CTRL_ENH_MODE 0x40
|
||||
#define TXQ_CTRL_TPD_FETCH_TH_SHIFT 8
|
||||
#define TXQ_CTRL_TPD_FETCH_TH_MASK 0x3F
|
||||
#define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16
|
||||
#define TXQ_CTRL_TXF_BURST_NUM_MASK 0xFFFF
|
||||
|
||||
/* Jumbo packet Threshold for task offload */
|
||||
#define REG_TX_JUMBO_TASK_TH_TPD_IPG 0x1584
|
||||
#define TX_JUMBO_TASK_TH_MASK 0x7FF
|
||||
#define TX_JUMBO_TASK_TH_SHIFT 0
|
||||
#define TX_TPD_MIN_IPG_MASK 0x1F
|
||||
#define TX_TPD_MIN_IPG_SHIFT 16
|
||||
|
||||
/* RXQ Control Register */
|
||||
#define REG_RXQ_CTRL 0x15A0
|
||||
#define RXQ_CTRL_RFD_BURST_NUM_SHIFT 0
|
||||
#define RXQ_CTRL_RFD_BURST_NUM_MASK 0xFF
|
||||
#define RXQ_CTRL_RRD_BURST_THRESH_SHIFT 8
|
||||
#define RXQ_CTRL_RRD_BURST_THRESH_MASK 0xFF
|
||||
#define RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT 16
|
||||
#define RXQ_CTRL_RFD_PREF_MIN_IPG_MASK 0x1F
|
||||
#define RXQ_CTRL_CUT_THRU_EN 0x40000000
|
||||
#define RXQ_CTRL_EN 0x80000000
|
||||
|
||||
/* Rx jumbo packet threshold and rrd retirement timer */
|
||||
#define REG_RXQ_JMBOSZ_RRDTIM 0x15A4
|
||||
#define RXQ_JMBOSZ_TH_MASK 0x7FF
|
||||
#define RXQ_JMBOSZ_TH_SHIFT 0
|
||||
#define RXQ_JMBO_LKAH_MASK 0xF
|
||||
#define RXQ_JMBO_LKAH_SHIFT 11
|
||||
#define RXQ_RRD_TIMER_MASK 0xFFFF
|
||||
#define RXQ_RRD_TIMER_SHIFT 16
|
||||
|
||||
/* RFD flow control register */
|
||||
#define REG_RXQ_RXF_PAUSE_THRESH 0x15A8
|
||||
#define RXQ_RXF_PAUSE_TH_HI_SHIFT 16
|
||||
#define RXQ_RXF_PAUSE_TH_HI_MASK 0xFFF
|
||||
#define RXQ_RXF_PAUSE_TH_LO_SHIFT 0
|
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#define RXQ_RXF_PAUSE_TH_LO_MASK 0xFFF
|
||||
|
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/* RRD flow control register */
|
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#define REG_RXQ_RRD_PAUSE_THRESH 0x15AC
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#define RXQ_RRD_PAUSE_TH_HI_SHIFT 0
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#define RXQ_RRD_PAUSE_TH_HI_MASK 0xFFF
|
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#define RXQ_RRD_PAUSE_TH_LO_SHIFT 16
|
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#define RXQ_RRD_PAUSE_TH_LO_MASK 0xFFF
|
||||
|
||||
/* DMA Engine Control Register */
|
||||
#define REG_DMA_CTRL 0x15C0
|
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#define DMA_CTRL_DMAR_IN_ORDER 0x1
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#define DMA_CTRL_DMAR_ENH_ORDER 0x2
|
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#define DMA_CTRL_DMAR_OUT_ORDER 0x4
|
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#define DMA_CTRL_RCB_VALUE 0x8
|
||||
#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
|
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#define DMA_CTRL_DMAR_BURST_LEN_MASK 7
|
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#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
|
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#define DMA_CTRL_DMAW_BURST_LEN_MASK 7
|
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#define DMA_CTRL_DMAR_EN 0x400
|
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#define DMA_CTRL_DMAW_EN 0x800
|
||||
|
||||
/* CMB/SMB Control Register */
|
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#define REG_CSMB_CTRL 0x15D0
|
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#define CSMB_CTRL_CMB_NOW 1
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#define CSMB_CTRL_SMB_NOW 2
|
||||
#define CSMB_CTRL_CMB_EN 4
|
||||
#define CSMB_CTRL_SMB_EN 8
|
||||
|
||||
/* CMB DMA Write Threshold Register */
|
||||
#define REG_CMB_WRITE_TH 0x15D4
|
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#define CMB_RRD_TH_SHIFT 0
|
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#define CMB_RRD_TH_MASK 0x7FF
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#define CMB_TPD_TH_SHIFT 16
|
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#define CMB_TPD_TH_MASK 0x7FF
|
||||
|
||||
/* RX/TX count-down timer to trigger CMB-write. 2us resolution. */
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#define REG_CMB_WRITE_TIMER 0x15D8
|
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#define CMB_RX_TM_SHIFT 0
|
||||
#define CMB_RX_TM_MASK 0xFFFF
|
||||
#define CMB_TX_TM_SHIFT 16
|
||||
#define CMB_TX_TM_MASK 0xFFFF
|
||||
|
||||
/* Number of packet received since last CMB write */
|
||||
#define REG_CMB_RX_PKT_CNT 0x15DC
|
||||
|
||||
/* Number of packet transmitted since last CMB write */
|
||||
#define REG_CMB_TX_PKT_CNT 0x15E0
|
||||
|
||||
/* SMB auto DMA timer register */
|
||||
#define REG_SMB_TIMER 0x15E4
|
||||
|
||||
/* Mailbox Register */
|
||||
#define REG_MAILBOX 0x15F0
|
||||
#define MB_RFD_PROD_INDX_SHIFT 0
|
||||
#define MB_RFD_PROD_INDX_MASK 0x7FF
|
||||
#define MB_RRD_CONS_INDX_SHIFT 11
|
||||
#define MB_RRD_CONS_INDX_MASK 0x7FF
|
||||
#define MB_TPD_PROD_INDX_SHIFT 22
|
||||
#define MB_TPD_PROD_INDX_MASK 0x3FF
|
||||
|
||||
/* Interrupt Status Register */
|
||||
#define ISR_SMB 0x1
|
||||
#define ISR_TIMER 0x2
|
||||
#define ISR_MANUAL 0x4
|
||||
#define ISR_RXF_OV 0x8
|
||||
#define ISR_RFD_UNRUN 0x10
|
||||
#define ISR_RRD_OV 0x20
|
||||
#define ISR_TXF_UNRUN 0x40
|
||||
#define ISR_LINK 0x80
|
||||
#define ISR_HOST_RFD_UNRUN 0x100
|
||||
#define ISR_HOST_RRD_OV 0x200
|
||||
#define ISR_DMAR_TO_RST 0x400
|
||||
#define ISR_DMAW_TO_RST 0x800
|
||||
#define ISR_GPHY 0x1000
|
||||
#define ISR_RX_PKT 0x10000
|
||||
#define ISR_TX_PKT 0x20000
|
||||
#define ISR_TX_DMA 0x40000
|
||||
#define ISR_RX_DMA 0x80000
|
||||
#define ISR_CMB_RX 0x100000
|
||||
#define ISR_CMB_TX 0x200000
|
||||
#define ISR_MAC_RX 0x400000
|
||||
#define ISR_MAC_TX 0x800000
|
||||
#define ISR_DIS_SMB 0x20000000
|
||||
#define ISR_DIS_DMA 0x40000000
|
||||
|
||||
/* Normal Interrupt mask */
|
||||
#define IMR_NORMAL_MASK (\
|
||||
ISR_SMB |\
|
||||
ISR_GPHY |\
|
||||
ISR_PHY_LINKDOWN|\
|
||||
ISR_DMAR_TO_RST |\
|
||||
ISR_DMAW_TO_RST |\
|
||||
ISR_CMB_TX |\
|
||||
ISR_CMB_RX)
|
||||
|
||||
/* Debug Interrupt Mask (enable all interrupt) */
|
||||
#define IMR_DEBUG_MASK (\
|
||||
ISR_SMB |\
|
||||
ISR_TIMER |\
|
||||
ISR_MANUAL |\
|
||||
ISR_RXF_OV |\
|
||||
ISR_RFD_UNRUN |\
|
||||
ISR_RRD_OV |\
|
||||
ISR_TXF_UNRUN |\
|
||||
ISR_LINK |\
|
||||
ISR_CMB_TX |\
|
||||
ISR_CMB_RX |\
|
||||
ISR_RX_PKT |\
|
||||
ISR_TX_PKT |\
|
||||
ISR_MAC_RX |\
|
||||
ISR_MAC_TX)
|
||||
|
||||
#define MEDIA_TYPE_1000M_FULL 1
|
||||
#define MEDIA_TYPE_100M_FULL 2
|
||||
#define MEDIA_TYPE_100M_HALF 3
|
||||
#define MEDIA_TYPE_10M_FULL 4
|
||||
#define MEDIA_TYPE_10M_HALF 5
|
||||
|
||||
#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* All but 1000-Half */
|
||||
|
||||
#define MAX_JUMBO_FRAME_SIZE 10240
|
||||
|
||||
#define ATL1_EEDUMP_LEN 48
|
||||
|
||||
/* Statistics counters collected by the MAC */
|
||||
struct stats_msg_block {
|
||||
/* rx */
|
||||
u32 rx_ok; /* good RX packets */
|
||||
u32 rx_bcast; /* good RX broadcast packets */
|
||||
u32 rx_mcast; /* good RX multicast packets */
|
||||
u32 rx_pause; /* RX pause frames */
|
||||
u32 rx_ctrl; /* RX control packets other than pause frames */
|
||||
u32 rx_fcs_err; /* RX packets with bad FCS */
|
||||
u32 rx_len_err; /* RX packets with length != actual size */
|
||||
u32 rx_byte_cnt; /* good bytes received. FCS is NOT included */
|
||||
u32 rx_runt; /* RX packets < 64 bytes with good FCS */
|
||||
u32 rx_frag; /* RX packets < 64 bytes with bad FCS */
|
||||
u32 rx_sz_64; /* 64 byte RX packets */
|
||||
u32 rx_sz_65_127;
|
||||
u32 rx_sz_128_255;
|
||||
u32 rx_sz_256_511;
|
||||
u32 rx_sz_512_1023;
|
||||
u32 rx_sz_1024_1518;
|
||||
u32 rx_sz_1519_max; /* 1519 byte to MTU RX packets */
|
||||
u32 rx_sz_ov; /* truncated RX packets > MTU */
|
||||
u32 rx_rxf_ov; /* frames dropped due to RX FIFO overflow */
|
||||
u32 rx_rrd_ov; /* frames dropped due to RRD overflow */
|
||||
u32 rx_align_err; /* alignment errors */
|
||||
u32 rx_bcast_byte_cnt; /* RX broadcast bytes, excluding FCS */
|
||||
u32 rx_mcast_byte_cnt; /* RX multicast bytes, excluding FCS */
|
||||
u32 rx_err_addr; /* packets dropped due to address filtering */
|
||||
|
||||
/* tx */
|
||||
u32 tx_ok; /* good TX packets */
|
||||
u32 tx_bcast; /* good TX broadcast packets */
|
||||
u32 tx_mcast; /* good TX multicast packets */
|
||||
u32 tx_pause; /* TX pause frames */
|
||||
u32 tx_exc_defer; /* TX packets deferred excessively */
|
||||
u32 tx_ctrl; /* TX control frames, excluding pause frames */
|
||||
u32 tx_defer; /* TX packets deferred */
|
||||
u32 tx_byte_cnt; /* bytes transmitted, FCS is NOT included */
|
||||
u32 tx_sz_64; /* 64 byte TX packets */
|
||||
u32 tx_sz_65_127;
|
||||
u32 tx_sz_128_255;
|
||||
u32 tx_sz_256_511;
|
||||
u32 tx_sz_512_1023;
|
||||
u32 tx_sz_1024_1518;
|
||||
u32 tx_sz_1519_max; /* 1519 byte to MTU TX packets */
|
||||
u32 tx_1_col; /* packets TX after a single collision */
|
||||
u32 tx_2_col; /* packets TX after multiple collisions */
|
||||
u32 tx_late_col; /* TX packets with late collisions */
|
||||
u32 tx_abort_col; /* TX packets aborted w/excessive collisions */
|
||||
u32 tx_underrun; /* TX packets aborted due to TX FIFO underrun
|
||||
* or TRD FIFO underrun */
|
||||
u32 tx_rd_eop; /* reads beyond the EOP into the next frame
|
||||
* when TRD was not written timely */
|
||||
u32 tx_len_err; /* TX packets where length != actual size */
|
||||
u32 tx_trunc; /* TX packets truncated due to size > MTU */
|
||||
u32 tx_bcast_byte; /* broadcast bytes transmitted, excluding FCS */
|
||||
u32 tx_mcast_byte; /* multicast bytes transmitted, excluding FCS */
|
||||
u32 smb_updated; /* 1: SMB Updated. This is used by software to
|
||||
* indicate the statistics update. Software
|
||||
* should clear this bit after retrieving the
|
||||
* statistics information. */
|
||||
};
|
||||
|
||||
/* Coalescing Message Block */
|
||||
struct coals_msg_block {
|
||||
u32 int_stats; /* interrupt status */
|
||||
u16 rrd_prod_idx; /* TRD Producer Index. */
|
||||
u16 rfd_cons_idx; /* RFD Consumer Index. */
|
||||
u16 update; /* Selene sets this bit every time it DMAs the
|
||||
* CMB to host memory. Software should clear
|
||||
* this bit when CMB info is processed. */
|
||||
u16 tpd_cons_idx; /* TPD Consumer Index. */
|
||||
};
|
||||
|
||||
/* RRD descriptor */
|
||||
struct rx_return_desc {
|
||||
u8 num_buf; /* Number of RFD buffers used by the received packet */
|
||||
u8 resved;
|
||||
u16 buf_indx; /* RFD Index of the first buffer */
|
||||
union {
|
||||
u32 valid;
|
||||
struct {
|
||||
u16 rx_chksum;
|
||||
u16 pkt_size;
|
||||
} xsum_sz;
|
||||
} xsz;
|
||||
|
||||
u16 pkt_flg; /* Packet flags */
|
||||
u16 err_flg; /* Error flags */
|
||||
u16 resved2;
|
||||
u16 vlan_tag; /* VLAN TAG */
|
||||
};
|
||||
|
||||
#define PACKET_FLAG_ETH_TYPE 0x0080
|
||||
#define PACKET_FLAG_VLAN_INS 0x0100
|
||||
#define PACKET_FLAG_ERR 0x0200
|
||||
#define PACKET_FLAG_IPV4 0x0400
|
||||
#define PACKET_FLAG_UDP 0x0800
|
||||
#define PACKET_FLAG_TCP 0x1000
|
||||
#define PACKET_FLAG_BCAST 0x2000
|
||||
#define PACKET_FLAG_MCAST 0x4000
|
||||
#define PACKET_FLAG_PAUSE 0x8000
|
||||
|
||||
#define ERR_FLAG_CRC 0x0001
|
||||
#define ERR_FLAG_CODE 0x0002
|
||||
#define ERR_FLAG_DRIBBLE 0x0004
|
||||
#define ERR_FLAG_RUNT 0x0008
|
||||
#define ERR_FLAG_OV 0x0010
|
||||
#define ERR_FLAG_TRUNC 0x0020
|
||||
#define ERR_FLAG_IP_CHKSUM 0x0040
|
||||
#define ERR_FLAG_L4_CHKSUM 0x0080
|
||||
#define ERR_FLAG_LEN 0x0100
|
||||
#define ERR_FLAG_DES_ADDR 0x0200
|
||||
|
||||
/* RFD descriptor */
|
||||
struct rx_free_desc {
|
||||
__le64 buffer_addr; /* Address of the descriptor's data buffer */
|
||||
__le16 buf_len; /* Size of the receive buffer in host memory */
|
||||
u16 coalese; /* Update consumer index to host after the
|
||||
* reception of this frame */
|
||||
/* __packed is required */
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
* The L1 transmit packet descriptor is comprised of four 32-bit words.
|
||||
*
|
||||
* 31 0
|
||||
* +---------------------------------------+
|
||||
* | Word 0: Buffer addr lo |
|
||||
* +---------------------------------------+
|
||||
* | Word 1: Buffer addr hi |
|
||||
* +---------------------------------------+
|
||||
* | Word 2 |
|
||||
* +---------------------------------------+
|
||||
* | Word 3 |
|
||||
* +---------------------------------------+
|
||||
*
|
||||
* Words 0 and 1 combine to form a 64-bit buffer address.
|
||||
*
|
||||
* Word 2 is self explanatory in the #define block below.
|
||||
*
|
||||
* Word 3 has two forms, depending upon the state of bits 3 and 4.
|
||||
* If bits 3 and 4 are both zero, then bits 14:31 are unused by the
|
||||
* hardware. Otherwise, if either bit 3 or 4 is set, the definition
|
||||
* of bits 14:31 vary according to the following depiction.
|
||||
*
|
||||
* 0 End of packet 0 End of packet
|
||||
* 1 Coalesce 1 Coalesce
|
||||
* 2 Insert VLAN tag 2 Insert VLAN tag
|
||||
* 3 Custom csum enable = 0 3 Custom csum enable = 1
|
||||
* 4 Segment enable = 1 4 Segment enable = 0
|
||||
* 5 Generate IP checksum 5 Generate IP checksum
|
||||
* 6 Generate TCP checksum 6 Generate TCP checksum
|
||||
* 7 Generate UDP checksum 7 Generate UDP checksum
|
||||
* 8 VLAN tagged 8 VLAN tagged
|
||||
* 9 Ethernet frame type 9 Ethernet frame type
|
||||
* 10-+ 10-+
|
||||
* 11 | IP hdr length (10:13) 11 | IP hdr length (10:13)
|
||||
* 12 | (num 32-bit words) 12 | (num 32-bit words)
|
||||
* 13-+ 13-+
|
||||
* 14-+ 14 Unused
|
||||
* 15 | TCP hdr length (14:17) 15 Unused
|
||||
* 16 | (num 32-bit words) 16-+
|
||||
* 17-+ 17 |
|
||||
* 18 Header TPD flag 18 |
|
||||
* 19-+ 19 | Payload offset
|
||||
* 20 | 20 | (16:23)
|
||||
* 21 | 21 |
|
||||
* 22 | 22 |
|
||||
* 23 | 23-+
|
||||
* 24 | 24-+
|
||||
* 25 | MSS (19:31) 25 |
|
||||
* 26 | 26 |
|
||||
* 27 | 27 | Custom csum offset
|
||||
* 28 | 28 | (24:31)
|
||||
* 29 | 29 |
|
||||
* 30 | 30 |
|
||||
* 31-+ 31-+
|
||||
*/
|
||||
|
||||
/* tpd word 2 */
|
||||
#define TPD_BUFLEN_MASK 0x3FFF
|
||||
#define TPD_BUFLEN_SHIFT 0
|
||||
#define TPD_DMAINT_MASK 0x0001
|
||||
#define TPD_DMAINT_SHIFT 14
|
||||
#define TPD_PKTNT_MASK 0x0001
|
||||
#define TPD_PKTINT_SHIFT 15
|
||||
#define TPD_VLANTAG_MASK 0xFFFF
|
||||
#define TPD_VLANTAG_SHIFT 16
|
||||
|
||||
/* tpd word 3 bits 0:13 */
|
||||
#define TPD_EOP_MASK 0x0001
|
||||
#define TPD_EOP_SHIFT 0
|
||||
#define TPD_COALESCE_MASK 0x0001
|
||||
#define TPD_COALESCE_SHIFT 1
|
||||
#define TPD_INS_VL_TAG_MASK 0x0001
|
||||
#define TPD_INS_VL_TAG_SHIFT 2
|
||||
#define TPD_CUST_CSUM_EN_MASK 0x0001
|
||||
#define TPD_CUST_CSUM_EN_SHIFT 3
|
||||
#define TPD_SEGMENT_EN_MASK 0x0001
|
||||
#define TPD_SEGMENT_EN_SHIFT 4
|
||||
#define TPD_IP_CSUM_MASK 0x0001
|
||||
#define TPD_IP_CSUM_SHIFT 5
|
||||
#define TPD_TCP_CSUM_MASK 0x0001
|
||||
#define TPD_TCP_CSUM_SHIFT 6
|
||||
#define TPD_UDP_CSUM_MASK 0x0001
|
||||
#define TPD_UDP_CSUM_SHIFT 7
|
||||
#define TPD_VL_TAGGED_MASK 0x0001
|
||||
#define TPD_VL_TAGGED_SHIFT 8
|
||||
#define TPD_ETHTYPE_MASK 0x0001
|
||||
#define TPD_ETHTYPE_SHIFT 9
|
||||
#define TPD_IPHL_MASK 0x000F
|
||||
#define TPD_IPHL_SHIFT 10
|
||||
|
||||
/* tpd word 3 bits 14:31 if segment enabled */
|
||||
#define TPD_TCPHDRLEN_MASK 0x000F
|
||||
#define TPD_TCPHDRLEN_SHIFT 14
|
||||
#define TPD_HDRFLAG_MASK 0x0001
|
||||
#define TPD_HDRFLAG_SHIFT 18
|
||||
#define TPD_MSS_MASK 0x1FFF
|
||||
#define TPD_MSS_SHIFT 19
|
||||
|
||||
/* tpd word 3 bits 16:31 if custom csum enabled */
|
||||
#define TPD_PLOADOFFSET_MASK 0x00FF
|
||||
#define TPD_PLOADOFFSET_SHIFT 16
|
||||
#define TPD_CCSUMOFFSET_MASK 0x00FF
|
||||
#define TPD_CCSUMOFFSET_SHIFT 24
|
||||
|
||||
struct tx_packet_desc {
|
||||
__le64 buffer_addr;
|
||||
__le32 word2;
|
||||
__le32 word3;
|
||||
};
|
||||
|
||||
/* DMA Order Settings */
|
||||
enum atl1_dma_order {
|
||||
atl1_dma_ord_in = 1,
|
||||
atl1_dma_ord_enh = 2,
|
||||
atl1_dma_ord_out = 4
|
||||
};
|
||||
|
||||
enum atl1_dma_rcb {
|
||||
atl1_rcb_64 = 0,
|
||||
atl1_rcb_128 = 1
|
||||
};
|
||||
|
||||
enum atl1_dma_req_block {
|
||||
atl1_dma_req_128 = 0,
|
||||
atl1_dma_req_256 = 1,
|
||||
atl1_dma_req_512 = 2,
|
||||
atl1_dma_req_1024 = 3,
|
||||
atl1_dma_req_2048 = 4,
|
||||
atl1_dma_req_4096 = 5
|
||||
};
|
||||
|
||||
#define ATL1_MAX_INTR 3
|
||||
#define ATL1_MAX_TX_BUF_LEN 0x3000 /* 12288 bytes */
|
||||
|
||||
#define ATL1_DEFAULT_TPD 256
|
||||
#define ATL1_MAX_TPD 1024
|
||||
#define ATL1_MIN_TPD 64
|
||||
#define ATL1_DEFAULT_RFD 512
|
||||
#define ATL1_MIN_RFD 128
|
||||
#define ATL1_MAX_RFD 2048
|
||||
#define ATL1_REG_COUNT 1538
|
||||
|
||||
#define ATL1_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
|
||||
#define ATL1_RFD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_free_desc)
|
||||
#define ATL1_TPD_DESC(R, i) ATL1_GET_DESC(R, i, struct tx_packet_desc)
|
||||
#define ATL1_RRD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_return_desc)
|
||||
|
||||
/*
|
||||
* atl1_ring_header represents a single, contiguous block of DMA space
|
||||
* mapped for the three descriptor rings (tpd, rfd, rrd) and the two
|
||||
* message blocks (cmb, smb) described below
|
||||
*/
|
||||
struct atl1_ring_header {
|
||||
void *desc; /* virtual address */
|
||||
dma_addr_t dma; /* physical address*/
|
||||
unsigned int size; /* length in bytes */
|
||||
};
|
||||
|
||||
/*
|
||||
* atl1_buffer is wrapper around a pointer to a socket buffer
|
||||
* so a DMA handle can be stored along with the skb
|
||||
*/
|
||||
struct atl1_buffer {
|
||||
struct sk_buff *skb; /* socket buffer */
|
||||
u16 length; /* rx buffer length */
|
||||
u16 alloced; /* 1 if skb allocated */
|
||||
dma_addr_t dma;
|
||||
};
|
||||
|
||||
/* transmit packet descriptor (tpd) ring */
|
||||
struct atl1_tpd_ring {
|
||||
void *desc; /* descriptor ring virtual address */
|
||||
dma_addr_t dma; /* descriptor ring physical address */
|
||||
u16 size; /* descriptor ring length in bytes */
|
||||
u16 count; /* number of descriptors in the ring */
|
||||
u16 hw_idx; /* hardware index */
|
||||
atomic_t next_to_clean;
|
||||
atomic_t next_to_use;
|
||||
struct atl1_buffer *buffer_info;
|
||||
};
|
||||
|
||||
/* receive free descriptor (rfd) ring */
|
||||
struct atl1_rfd_ring {
|
||||
void *desc; /* descriptor ring virtual address */
|
||||
dma_addr_t dma; /* descriptor ring physical address */
|
||||
u16 size; /* descriptor ring length in bytes */
|
||||
u16 count; /* number of descriptors in the ring */
|
||||
atomic_t next_to_use;
|
||||
u16 next_to_clean;
|
||||
struct atl1_buffer *buffer_info;
|
||||
};
|
||||
|
||||
/* receive return descriptor (rrd) ring */
|
||||
struct atl1_rrd_ring {
|
||||
void *desc; /* descriptor ring virtual address */
|
||||
dma_addr_t dma; /* descriptor ring physical address */
|
||||
unsigned int size; /* descriptor ring length in bytes */
|
||||
u16 count; /* number of descriptors in the ring */
|
||||
u16 next_to_use;
|
||||
atomic_t next_to_clean;
|
||||
};
|
||||
|
||||
/* coalescing message block (cmb) */
|
||||
struct atl1_cmb {
|
||||
struct coals_msg_block *cmb;
|
||||
dma_addr_t dma;
|
||||
};
|
||||
|
||||
/* statistics message block (smb) */
|
||||
struct atl1_smb {
|
||||
struct stats_msg_block *smb;
|
||||
dma_addr_t dma;
|
||||
};
|
||||
|
||||
/* Statistics counters */
|
||||
struct atl1_sft_stats {
|
||||
u64 rx_packets;
|
||||
u64 tx_packets;
|
||||
u64 rx_bytes;
|
||||
u64 tx_bytes;
|
||||
u64 multicast;
|
||||
u64 collisions;
|
||||
u64 rx_errors;
|
||||
u64 rx_length_errors;
|
||||
u64 rx_crc_errors;
|
||||
u64 rx_frame_errors;
|
||||
u64 rx_fifo_errors;
|
||||
u64 rx_missed_errors;
|
||||
u64 tx_errors;
|
||||
u64 tx_fifo_errors;
|
||||
u64 tx_aborted_errors;
|
||||
u64 tx_window_errors;
|
||||
u64 tx_carrier_errors;
|
||||
u64 tx_pause; /* TX pause frames */
|
||||
u64 excecol; /* TX packets w/ excessive collisions */
|
||||
u64 deffer; /* TX packets deferred */
|
||||
u64 scc; /* packets TX after a single collision */
|
||||
u64 mcc; /* packets TX after multiple collisions */
|
||||
u64 latecol; /* TX packets w/ late collisions */
|
||||
u64 tx_underun; /* TX packets aborted due to TX FIFO underrun
|
||||
* or TRD FIFO underrun */
|
||||
u64 tx_trunc; /* TX packets truncated due to size > MTU */
|
||||
u64 rx_pause; /* num Pause packets received. */
|
||||
u64 rx_rrd_ov;
|
||||
u64 rx_trunc;
|
||||
};
|
||||
|
||||
/* hardware structure */
|
||||
struct atl1_hw {
|
||||
u8 __iomem *hw_addr;
|
||||
struct atl1_adapter *back;
|
||||
enum atl1_dma_order dma_ord;
|
||||
enum atl1_dma_rcb rcb_value;
|
||||
enum atl1_dma_req_block dmar_block;
|
||||
enum atl1_dma_req_block dmaw_block;
|
||||
u8 preamble_len;
|
||||
u8 max_retry;
|
||||
u8 jam_ipg; /* IPG to start JAM for collision based flow
|
||||
* control in half-duplex mode. In units of
|
||||
* 8-bit time */
|
||||
u8 ipgt; /* Desired back to back inter-packet gap.
|
||||
* The default is 96-bit time */
|
||||
u8 min_ifg; /* Minimum number of IFG to enforce in between
|
||||
* receive frames. Frame gap below such IFP
|
||||
* is dropped */
|
||||
u8 ipgr1; /* 64bit Carrier-Sense window */
|
||||
u8 ipgr2; /* 96-bit IPG window */
|
||||
u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned
|
||||
* burst. Each TPD is 16 bytes long */
|
||||
u8 rfd_burst; /* Number of RFD to prefetch in cache-aligned
|
||||
* burst. Each RFD is 12 bytes long */
|
||||
u8 rfd_fetch_gap;
|
||||
u8 rrd_burst; /* Threshold number of RRDs that can be retired
|
||||
* in a burst. Each RRD is 16 bytes long */
|
||||
u8 tpd_fetch_th;
|
||||
u8 tpd_fetch_gap;
|
||||
u16 tx_jumbo_task_th;
|
||||
u16 txf_burst; /* Number of data bytes to read in a cache-
|
||||
* aligned burst. Each SRAM entry is 8 bytes */
|
||||
u16 rx_jumbo_th; /* Jumbo packet size for non-VLAN packet. VLAN
|
||||
* packets should add 4 bytes */
|
||||
u16 rx_jumbo_lkah;
|
||||
u16 rrd_ret_timer; /* RRD retirement timer. Decrement by 1 after
|
||||
* every 512ns passes. */
|
||||
u16 lcol; /* Collision Window */
|
||||
|
||||
u16 cmb_tpd;
|
||||
u16 cmb_rrd;
|
||||
u16 cmb_rx_timer;
|
||||
u16 cmb_tx_timer;
|
||||
u32 smb_timer;
|
||||
u16 media_type;
|
||||
u16 autoneg_advertised;
|
||||
|
||||
u16 mii_autoneg_adv_reg;
|
||||
u16 mii_1000t_ctrl_reg;
|
||||
|
||||
u32 max_frame_size;
|
||||
u32 min_frame_size;
|
||||
|
||||
u16 dev_rev;
|
||||
|
||||
/* spi flash */
|
||||
u8 flash_vendor;
|
||||
|
||||
u8 mac_addr[ETH_ALEN];
|
||||
u8 perm_mac_addr[ETH_ALEN];
|
||||
|
||||
bool phy_configured;
|
||||
};
|
||||
|
||||
struct atl1_adapter {
|
||||
struct net_device *netdev;
|
||||
struct pci_dev *pdev;
|
||||
|
||||
struct atl1_sft_stats soft_stats;
|
||||
u32 rx_buffer_len;
|
||||
u32 wol;
|
||||
u16 link_speed;
|
||||
u16 link_duplex;
|
||||
spinlock_t lock;
|
||||
struct work_struct tx_timeout_task;
|
||||
struct work_struct link_chg_task;
|
||||
struct work_struct pcie_dma_to_rst_task;
|
||||
|
||||
struct timer_list phy_config_timer;
|
||||
bool phy_timer_pending;
|
||||
|
||||
/* all descriptor rings' memory */
|
||||
struct atl1_ring_header ring_header;
|
||||
|
||||
/* TX */
|
||||
struct atl1_tpd_ring tpd_ring;
|
||||
spinlock_t mb_lock;
|
||||
|
||||
/* RX */
|
||||
struct atl1_rfd_ring rfd_ring;
|
||||
struct atl1_rrd_ring rrd_ring;
|
||||
u64 hw_csum_err;
|
||||
u64 hw_csum_good;
|
||||
u32 msg_enable;
|
||||
u16 imt; /* interrupt moderator timer (2us resolution) */
|
||||
u16 ict; /* interrupt clear timer (2us resolution */
|
||||
struct mii_if_info mii; /* MII interface info */
|
||||
|
||||
u32 bd_number; /* board number */
|
||||
bool pci_using_64;
|
||||
struct atl1_hw hw;
|
||||
struct atl1_smb smb;
|
||||
struct atl1_cmb cmb;
|
||||
};
|
||||
|
||||
#endif /* ATL1_H */
|
||||
3119
drivers/net/ethernet/atheros/atlx/atl2.c
Normal file
3119
drivers/net/ethernet/atheros/atlx/atl2.c
Normal file
File diff suppressed because it is too large
Load Diff
525
drivers/net/ethernet/atheros/atlx/atl2.h
Normal file
525
drivers/net/ethernet/atheros/atlx/atl2.h
Normal file
@@ -0,0 +1,525 @@
|
||||
/* atl2.h -- atl2 driver definitions
|
||||
*
|
||||
* Copyright(c) 2007 Atheros Corporation. All rights reserved.
|
||||
* Copyright(c) 2006 xiong huang <xiong.huang@atheros.com>
|
||||
* Copyright(c) 2007 Chris Snook <csnook@redhat.com>
|
||||
*
|
||||
* Derived from Intel e1000 driver
|
||||
* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59
|
||||
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef _ATL2_H_
|
||||
#define _ATL2_H_
|
||||
|
||||
#include <linux/atomic.h>
|
||||
#include <linux/netdevice.h>
|
||||
|
||||
#ifndef _ATL2_HW_H_
|
||||
#define _ATL2_HW_H_
|
||||
|
||||
#ifndef _ATL2_OSDEP_H_
|
||||
#define _ATL2_OSDEP_H_
|
||||
|
||||
#include <linux/pci.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/if_ether.h>
|
||||
|
||||
#include "atlx.h"
|
||||
|
||||
#ifdef ETHTOOL_OPS_COMPAT
|
||||
extern int ethtool_ioctl(struct ifreq *ifr);
|
||||
#endif
|
||||
|
||||
#define PCI_COMMAND_REGISTER PCI_COMMAND
|
||||
#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
|
||||
#define ETH_ADDR_LEN ETH_ALEN
|
||||
|
||||
#define ATL2_WRITE_REG(a, reg, value) (iowrite32((value), \
|
||||
((a)->hw_addr + (reg))))
|
||||
|
||||
#define ATL2_WRITE_FLUSH(a) (ioread32((a)->hw_addr))
|
||||
|
||||
#define ATL2_READ_REG(a, reg) (ioread32((a)->hw_addr + (reg)))
|
||||
|
||||
#define ATL2_WRITE_REGB(a, reg, value) (iowrite8((value), \
|
||||
((a)->hw_addr + (reg))))
|
||||
|
||||
#define ATL2_READ_REGB(a, reg) (ioread8((a)->hw_addr + (reg)))
|
||||
|
||||
#define ATL2_WRITE_REGW(a, reg, value) (iowrite16((value), \
|
||||
((a)->hw_addr + (reg))))
|
||||
|
||||
#define ATL2_READ_REGW(a, reg) (ioread16((a)->hw_addr + (reg)))
|
||||
|
||||
#define ATL2_WRITE_REG_ARRAY(a, reg, offset, value) \
|
||||
(iowrite32((value), (((a)->hw_addr + (reg)) + ((offset) << 2))))
|
||||
|
||||
#define ATL2_READ_REG_ARRAY(a, reg, offset) \
|
||||
(ioread32(((a)->hw_addr + (reg)) + ((offset) << 2)))
|
||||
|
||||
#endif /* _ATL2_OSDEP_H_ */
|
||||
|
||||
struct atl2_adapter;
|
||||
struct atl2_hw;
|
||||
|
||||
/* function prototype */
|
||||
static s32 atl2_reset_hw(struct atl2_hw *hw);
|
||||
static s32 atl2_read_mac_addr(struct atl2_hw *hw);
|
||||
static s32 atl2_init_hw(struct atl2_hw *hw);
|
||||
static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,
|
||||
u16 *duplex);
|
||||
static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr);
|
||||
static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value);
|
||||
static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data);
|
||||
static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data);
|
||||
static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value);
|
||||
static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value);
|
||||
static void atl2_set_mac_addr(struct atl2_hw *hw);
|
||||
static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue);
|
||||
static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value);
|
||||
static s32 atl2_phy_init(struct atl2_hw *hw);
|
||||
static int atl2_check_eeprom_exist(struct atl2_hw *hw);
|
||||
static void atl2_force_ps(struct atl2_hw *hw);
|
||||
|
||||
/* register definition */
|
||||
|
||||
/* Block IDLE Status Register */
|
||||
#define IDLE_STATUS_RXMAC 1 /* 1: RXMAC is non-IDLE */
|
||||
#define IDLE_STATUS_TXMAC 2 /* 1: TXMAC is non-IDLE */
|
||||
#define IDLE_STATUS_DMAR 8 /* 1: DMAR is non-IDLE */
|
||||
#define IDLE_STATUS_DMAW 4 /* 1: DMAW is non-IDLE */
|
||||
|
||||
/* MDIO Control Register */
|
||||
#define MDIO_WAIT_TIMES 10
|
||||
|
||||
/* MAC Control Register */
|
||||
#define MAC_CTRL_DBG_TX_BKPRESURE 0x100000 /* 1: TX max backoff */
|
||||
#define MAC_CTRL_MACLP_CLK_PHY 0x8000000 /* 1: 25MHz from phy */
|
||||
#define MAC_CTRL_HALF_LEFT_BUF_SHIFT 28
|
||||
#define MAC_CTRL_HALF_LEFT_BUF_MASK 0xF /* MAC retry buf x32B */
|
||||
|
||||
/* Internal SRAM Partition Register */
|
||||
#define REG_SRAM_TXRAM_END 0x1500 /* Internal tail address of TXRAM
|
||||
* default: 2byte*1024 */
|
||||
#define REG_SRAM_RXRAM_END 0x1502 /* Internal tail address of RXRAM
|
||||
* default: 2byte*1024 */
|
||||
|
||||
/* Descriptor Control register */
|
||||
#define REG_TXD_BASE_ADDR_LO 0x1544 /* The base address of the Transmit
|
||||
* Data Mem low 32-bit(dword align) */
|
||||
#define REG_TXD_MEM_SIZE 0x1548 /* Transmit Data Memory size(by
|
||||
* double word , max 256KB) */
|
||||
#define REG_TXS_BASE_ADDR_LO 0x154C /* The base address of the Transmit
|
||||
* Status Memory low 32-bit(dword word
|
||||
* align) */
|
||||
#define REG_TXS_MEM_SIZE 0x1550 /* double word unit, max 4*2047
|
||||
* bytes. */
|
||||
#define REG_RXD_BASE_ADDR_LO 0x1554 /* The base address of the Transmit
|
||||
* Status Memory low 32-bit(unit 8
|
||||
* bytes) */
|
||||
#define REG_RXD_BUF_NUM 0x1558 /* Receive Data & Status Memory buffer
|
||||
* number (unit 1536bytes, max
|
||||
* 1536*2047) */
|
||||
|
||||
/* DMAR Control Register */
|
||||
#define REG_DMAR 0x1580
|
||||
#define DMAR_EN 0x1 /* 1: Enable DMAR */
|
||||
|
||||
/* TX Cur-Through (early tx threshold) Control Register */
|
||||
#define REG_TX_CUT_THRESH 0x1590 /* TxMac begin transmit packet
|
||||
* threshold(unit word) */
|
||||
|
||||
/* DMAW Control Register */
|
||||
#define REG_DMAW 0x15A0
|
||||
#define DMAW_EN 0x1
|
||||
|
||||
/* Flow control register */
|
||||
#define REG_PAUSE_ON_TH 0x15A8 /* RXD high watermark of overflow
|
||||
* threshold configuration register */
|
||||
#define REG_PAUSE_OFF_TH 0x15AA /* RXD lower watermark of overflow
|
||||
* threshold configuration register */
|
||||
|
||||
/* Mailbox Register */
|
||||
#define REG_MB_TXD_WR_IDX 0x15f0 /* double word align */
|
||||
#define REG_MB_RXD_RD_IDX 0x15F4 /* RXD Read index (unit: 1536byets) */
|
||||
|
||||
/* Interrupt Status Register */
|
||||
#define ISR_TIMER 1 /* Interrupt when Timer counts down to zero */
|
||||
#define ISR_MANUAL 2 /* Software manual interrupt, for debug. Set
|
||||
* when SW_MAN_INT_EN is set in Table 51
|
||||
* Selene Master Control Register
|
||||
* (Offset 0x1400). */
|
||||
#define ISR_RXF_OV 4 /* RXF overflow interrupt */
|
||||
#define ISR_TXF_UR 8 /* TXF underrun interrupt */
|
||||
#define ISR_TXS_OV 0x10 /* Internal transmit status buffer full
|
||||
* interrupt */
|
||||
#define ISR_RXS_OV 0x20 /* Internal receive status buffer full
|
||||
* interrupt */
|
||||
#define ISR_LINK_CHG 0x40 /* Link Status Change Interrupt */
|
||||
#define ISR_HOST_TXD_UR 0x80
|
||||
#define ISR_HOST_RXD_OV 0x100 /* Host rx data memory full , one pulse */
|
||||
#define ISR_DMAR_TO_RST 0x200 /* DMAR op timeout interrupt. SW should
|
||||
* do Reset */
|
||||
#define ISR_DMAW_TO_RST 0x400
|
||||
#define ISR_PHY 0x800 /* phy interrupt */
|
||||
#define ISR_TS_UPDATE 0x10000 /* interrupt after new tx pkt status written
|
||||
* to host */
|
||||
#define ISR_RS_UPDATE 0x20000 /* interrupt ater new rx pkt status written
|
||||
* to host. */
|
||||
#define ISR_TX_EARLY 0x40000 /* interrupt when txmac begin transmit one
|
||||
* packet */
|
||||
|
||||
#define ISR_TX_EVENT (ISR_TXF_UR | ISR_TXS_OV | ISR_HOST_TXD_UR |\
|
||||
ISR_TS_UPDATE | ISR_TX_EARLY)
|
||||
#define ISR_RX_EVENT (ISR_RXF_OV | ISR_RXS_OV | ISR_HOST_RXD_OV |\
|
||||
ISR_RS_UPDATE)
|
||||
|
||||
#define IMR_NORMAL_MASK (\
|
||||
/*ISR_LINK_CHG |*/\
|
||||
ISR_MANUAL |\
|
||||
ISR_DMAR_TO_RST |\
|
||||
ISR_DMAW_TO_RST |\
|
||||
ISR_PHY |\
|
||||
ISR_PHY_LINKDOWN |\
|
||||
ISR_TS_UPDATE |\
|
||||
ISR_RS_UPDATE)
|
||||
|
||||
/* Receive MAC Statistics Registers */
|
||||
#define REG_STS_RX_PAUSE 0x1700 /* Num pause packets received */
|
||||
#define REG_STS_RXD_OV 0x1704 /* Num frames dropped due to RX
|
||||
* FIFO overflow */
|
||||
#define REG_STS_RXS_OV 0x1708 /* Num frames dropped due to RX
|
||||
* Status Buffer Overflow */
|
||||
#define REG_STS_RX_FILTER 0x170C /* Num packets dropped due to
|
||||
* address filtering */
|
||||
|
||||
/* MII definitions */
|
||||
|
||||
/* PHY Common Register */
|
||||
#define MII_SMARTSPEED 0x14
|
||||
#define MII_DBG_ADDR 0x1D
|
||||
#define MII_DBG_DATA 0x1E
|
||||
|
||||
/* PCI Command Register Bit Definitions */
|
||||
#define PCI_REG_COMMAND 0x04
|
||||
#define CMD_IO_SPACE 0x0001
|
||||
#define CMD_MEMORY_SPACE 0x0002
|
||||
#define CMD_BUS_MASTER 0x0004
|
||||
|
||||
#define MEDIA_TYPE_100M_FULL 1
|
||||
#define MEDIA_TYPE_100M_HALF 2
|
||||
#define MEDIA_TYPE_10M_FULL 3
|
||||
#define MEDIA_TYPE_10M_HALF 4
|
||||
|
||||
#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x000F /* Everything */
|
||||
|
||||
/* The size (in bytes) of a ethernet packet */
|
||||
#define ENET_HEADER_SIZE 14
|
||||
#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* with FCS */
|
||||
#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* with FCS */
|
||||
#define ETHERNET_FCS_SIZE 4
|
||||
#define MAX_JUMBO_FRAME_SIZE 0x2000
|
||||
#define VLAN_SIZE 4
|
||||
|
||||
struct tx_pkt_header {
|
||||
unsigned pkt_size:11;
|
||||
unsigned:4; /* reserved */
|
||||
unsigned ins_vlan:1; /* txmac should insert vlan */
|
||||
unsigned short vlan; /* vlan tag */
|
||||
};
|
||||
/* FIXME: replace above bitfields with MASK/SHIFT defines below */
|
||||
#define TX_PKT_HEADER_SIZE_MASK 0x7FF
|
||||
#define TX_PKT_HEADER_SIZE_SHIFT 0
|
||||
#define TX_PKT_HEADER_INS_VLAN_MASK 0x1
|
||||
#define TX_PKT_HEADER_INS_VLAN_SHIFT 15
|
||||
#define TX_PKT_HEADER_VLAN_TAG_MASK 0xFFFF
|
||||
#define TX_PKT_HEADER_VLAN_TAG_SHIFT 16
|
||||
|
||||
struct tx_pkt_status {
|
||||
unsigned pkt_size:11;
|
||||
unsigned:5; /* reserved */
|
||||
unsigned ok:1; /* current packet transmitted without error */
|
||||
unsigned bcast:1; /* broadcast packet */
|
||||
unsigned mcast:1; /* multicast packet */
|
||||
unsigned pause:1; /* transmiited a pause frame */
|
||||
unsigned ctrl:1;
|
||||
unsigned defer:1; /* current packet is xmitted with defer */
|
||||
unsigned exc_defer:1;
|
||||
unsigned single_col:1;
|
||||
unsigned multi_col:1;
|
||||
unsigned late_col:1;
|
||||
unsigned abort_col:1;
|
||||
unsigned underun:1; /* current packet is aborted
|
||||
* due to txram underrun */
|
||||
unsigned:3; /* reserved */
|
||||
unsigned update:1; /* always 1'b1 in tx_status_buf */
|
||||
};
|
||||
/* FIXME: replace above bitfields with MASK/SHIFT defines below */
|
||||
#define TX_PKT_STATUS_SIZE_MASK 0x7FF
|
||||
#define TX_PKT_STATUS_SIZE_SHIFT 0
|
||||
#define TX_PKT_STATUS_OK_MASK 0x1
|
||||
#define TX_PKT_STATUS_OK_SHIFT 16
|
||||
#define TX_PKT_STATUS_BCAST_MASK 0x1
|
||||
#define TX_PKT_STATUS_BCAST_SHIFT 17
|
||||
#define TX_PKT_STATUS_MCAST_MASK 0x1
|
||||
#define TX_PKT_STATUS_MCAST_SHIFT 18
|
||||
#define TX_PKT_STATUS_PAUSE_MASK 0x1
|
||||
#define TX_PKT_STATUS_PAUSE_SHIFT 19
|
||||
#define TX_PKT_STATUS_CTRL_MASK 0x1
|
||||
#define TX_PKT_STATUS_CTRL_SHIFT 20
|
||||
#define TX_PKT_STATUS_DEFER_MASK 0x1
|
||||
#define TX_PKT_STATUS_DEFER_SHIFT 21
|
||||
#define TX_PKT_STATUS_EXC_DEFER_MASK 0x1
|
||||
#define TX_PKT_STATUS_EXC_DEFER_SHIFT 22
|
||||
#define TX_PKT_STATUS_SINGLE_COL_MASK 0x1
|
||||
#define TX_PKT_STATUS_SINGLE_COL_SHIFT 23
|
||||
#define TX_PKT_STATUS_MULTI_COL_MASK 0x1
|
||||
#define TX_PKT_STATUS_MULTI_COL_SHIFT 24
|
||||
#define TX_PKT_STATUS_LATE_COL_MASK 0x1
|
||||
#define TX_PKT_STATUS_LATE_COL_SHIFT 25
|
||||
#define TX_PKT_STATUS_ABORT_COL_MASK 0x1
|
||||
#define TX_PKT_STATUS_ABORT_COL_SHIFT 26
|
||||
#define TX_PKT_STATUS_UNDERRUN_MASK 0x1
|
||||
#define TX_PKT_STATUS_UNDERRUN_SHIFT 27
|
||||
#define TX_PKT_STATUS_UPDATE_MASK 0x1
|
||||
#define TX_PKT_STATUS_UPDATE_SHIFT 31
|
||||
|
||||
struct rx_pkt_status {
|
||||
unsigned pkt_size:11; /* packet size, max 2047 bytes */
|
||||
unsigned:5; /* reserved */
|
||||
unsigned ok:1; /* current packet received ok without error */
|
||||
unsigned bcast:1; /* current packet is broadcast */
|
||||
unsigned mcast:1; /* current packet is multicast */
|
||||
unsigned pause:1;
|
||||
unsigned ctrl:1;
|
||||
unsigned crc:1; /* received a packet with crc error */
|
||||
unsigned code:1; /* received a packet with code error */
|
||||
unsigned runt:1; /* received a packet less than 64 bytes
|
||||
* with good crc */
|
||||
unsigned frag:1; /* received a packet less than 64 bytes
|
||||
* with bad crc */
|
||||
unsigned trunc:1; /* current frame truncated due to rxram full */
|
||||
unsigned align:1; /* this packet is alignment error */
|
||||
unsigned vlan:1; /* this packet has vlan */
|
||||
unsigned:3; /* reserved */
|
||||
unsigned update:1;
|
||||
unsigned short vtag; /* vlan tag */
|
||||
unsigned:16;
|
||||
};
|
||||
/* FIXME: replace above bitfields with MASK/SHIFT defines below */
|
||||
#define RX_PKT_STATUS_SIZE_MASK 0x7FF
|
||||
#define RX_PKT_STATUS_SIZE_SHIFT 0
|
||||
#define RX_PKT_STATUS_OK_MASK 0x1
|
||||
#define RX_PKT_STATUS_OK_SHIFT 16
|
||||
#define RX_PKT_STATUS_BCAST_MASK 0x1
|
||||
#define RX_PKT_STATUS_BCAST_SHIFT 17
|
||||
#define RX_PKT_STATUS_MCAST_MASK 0x1
|
||||
#define RX_PKT_STATUS_MCAST_SHIFT 18
|
||||
#define RX_PKT_STATUS_PAUSE_MASK 0x1
|
||||
#define RX_PKT_STATUS_PAUSE_SHIFT 19
|
||||
#define RX_PKT_STATUS_CTRL_MASK 0x1
|
||||
#define RX_PKT_STATUS_CTRL_SHIFT 20
|
||||
#define RX_PKT_STATUS_CRC_MASK 0x1
|
||||
#define RX_PKT_STATUS_CRC_SHIFT 21
|
||||
#define RX_PKT_STATUS_CODE_MASK 0x1
|
||||
#define RX_PKT_STATUS_CODE_SHIFT 22
|
||||
#define RX_PKT_STATUS_RUNT_MASK 0x1
|
||||
#define RX_PKT_STATUS_RUNT_SHIFT 23
|
||||
#define RX_PKT_STATUS_FRAG_MASK 0x1
|
||||
#define RX_PKT_STATUS_FRAG_SHIFT 24
|
||||
#define RX_PKT_STATUS_TRUNK_MASK 0x1
|
||||
#define RX_PKT_STATUS_TRUNK_SHIFT 25
|
||||
#define RX_PKT_STATUS_ALIGN_MASK 0x1
|
||||
#define RX_PKT_STATUS_ALIGN_SHIFT 26
|
||||
#define RX_PKT_STATUS_VLAN_MASK 0x1
|
||||
#define RX_PKT_STATUS_VLAN_SHIFT 27
|
||||
#define RX_PKT_STATUS_UPDATE_MASK 0x1
|
||||
#define RX_PKT_STATUS_UPDATE_SHIFT 31
|
||||
#define RX_PKT_STATUS_VLAN_TAG_MASK 0xFFFF
|
||||
#define RX_PKT_STATUS_VLAN_TAG_SHIFT 32
|
||||
|
||||
struct rx_desc {
|
||||
struct rx_pkt_status status;
|
||||
unsigned char packet[1536-sizeof(struct rx_pkt_status)];
|
||||
};
|
||||
|
||||
enum atl2_speed_duplex {
|
||||
atl2_10_half = 0,
|
||||
atl2_10_full = 1,
|
||||
atl2_100_half = 2,
|
||||
atl2_100_full = 3
|
||||
};
|
||||
|
||||
struct atl2_spi_flash_dev {
|
||||
const char *manu_name; /* manufacturer id */
|
||||
/* op-code */
|
||||
u8 cmdWRSR;
|
||||
u8 cmdREAD;
|
||||
u8 cmdPROGRAM;
|
||||
u8 cmdWREN;
|
||||
u8 cmdWRDI;
|
||||
u8 cmdRDSR;
|
||||
u8 cmdRDID;
|
||||
u8 cmdSECTOR_ERASE;
|
||||
u8 cmdCHIP_ERASE;
|
||||
};
|
||||
|
||||
/* Structure containing variables used by the shared code (atl2_hw.c) */
|
||||
struct atl2_hw {
|
||||
u8 __iomem *hw_addr;
|
||||
void *back;
|
||||
|
||||
u8 preamble_len;
|
||||
u8 max_retry; /* Retransmission maximum, afterwards the
|
||||
* packet will be discarded. */
|
||||
u8 jam_ipg; /* IPG to start JAM for collision based flow
|
||||
* control in half-duplex mode. In unit of
|
||||
* 8-bit time. */
|
||||
u8 ipgt; /* Desired back to back inter-packet gap. The
|
||||
* default is 96-bit time. */
|
||||
u8 min_ifg; /* Minimum number of IFG to enforce in between
|
||||
* RX frames. Frame gap below such IFP is
|
||||
* dropped. */
|
||||
u8 ipgr1; /* 64bit Carrier-Sense window */
|
||||
u8 ipgr2; /* 96-bit IPG window */
|
||||
u8 retry_buf; /* When half-duplex mode, should hold some
|
||||
* bytes for mac retry . (8*4bytes unit) */
|
||||
|
||||
u16 fc_rxd_hi;
|
||||
u16 fc_rxd_lo;
|
||||
u16 lcol; /* Collision Window */
|
||||
u16 max_frame_size;
|
||||
|
||||
u16 MediaType;
|
||||
u16 autoneg_advertised;
|
||||
u16 pci_cmd_word;
|
||||
|
||||
u16 mii_autoneg_adv_reg;
|
||||
|
||||
u32 mem_rang;
|
||||
u32 txcw;
|
||||
u32 mc_filter_type;
|
||||
u32 num_mc_addrs;
|
||||
u32 collision_delta;
|
||||
u32 tx_packet_delta;
|
||||
u16 phy_spd_default;
|
||||
|
||||
u16 device_id;
|
||||
u16 vendor_id;
|
||||
u16 subsystem_id;
|
||||
u16 subsystem_vendor_id;
|
||||
u8 revision_id;
|
||||
|
||||
/* spi flash */
|
||||
u8 flash_vendor;
|
||||
|
||||
u8 dma_fairness;
|
||||
u8 mac_addr[NODE_ADDRESS_SIZE];
|
||||
u8 perm_mac_addr[NODE_ADDRESS_SIZE];
|
||||
|
||||
/* FIXME */
|
||||
/* bool phy_preamble_sup; */
|
||||
bool phy_configured;
|
||||
};
|
||||
|
||||
#endif /* _ATL2_HW_H_ */
|
||||
|
||||
struct atl2_ring_header {
|
||||
/* pointer to the descriptor ring memory */
|
||||
void *desc;
|
||||
/* physical address of the descriptor ring */
|
||||
dma_addr_t dma;
|
||||
/* length of descriptor ring in bytes */
|
||||
unsigned int size;
|
||||
};
|
||||
|
||||
/* board specific private data structure */
|
||||
struct atl2_adapter {
|
||||
/* OS defined structs */
|
||||
struct net_device *netdev;
|
||||
struct pci_dev *pdev;
|
||||
u32 wol;
|
||||
u16 link_speed;
|
||||
u16 link_duplex;
|
||||
|
||||
spinlock_t stats_lock;
|
||||
|
||||
struct work_struct reset_task;
|
||||
struct work_struct link_chg_task;
|
||||
struct timer_list watchdog_timer;
|
||||
struct timer_list phy_config_timer;
|
||||
|
||||
unsigned long cfg_phy;
|
||||
bool mac_disabled;
|
||||
|
||||
/* All Descriptor memory */
|
||||
dma_addr_t ring_dma;
|
||||
void *ring_vir_addr;
|
||||
int ring_size;
|
||||
|
||||
struct tx_pkt_header *txd_ring;
|
||||
dma_addr_t txd_dma;
|
||||
|
||||
struct tx_pkt_status *txs_ring;
|
||||
dma_addr_t txs_dma;
|
||||
|
||||
struct rx_desc *rxd_ring;
|
||||
dma_addr_t rxd_dma;
|
||||
|
||||
u32 txd_ring_size; /* bytes per unit */
|
||||
u32 txs_ring_size; /* dwords per unit */
|
||||
u32 rxd_ring_size; /* 1536 bytes per unit */
|
||||
|
||||
/* read /write ptr: */
|
||||
/* host */
|
||||
u32 txd_write_ptr;
|
||||
u32 txs_next_clear;
|
||||
u32 rxd_read_ptr;
|
||||
|
||||
/* nic */
|
||||
atomic_t txd_read_ptr;
|
||||
atomic_t txs_write_ptr;
|
||||
u32 rxd_write_ptr;
|
||||
|
||||
/* Interrupt Moderator timer ( 2us resolution) */
|
||||
u16 imt;
|
||||
/* Interrupt Clear timer (2us resolution) */
|
||||
u16 ict;
|
||||
|
||||
unsigned long flags;
|
||||
/* structs defined in atl2_hw.h */
|
||||
u32 bd_number; /* board number */
|
||||
bool pci_using_64;
|
||||
bool have_msi;
|
||||
struct atl2_hw hw;
|
||||
|
||||
u32 usr_cmd;
|
||||
/* FIXME */
|
||||
/* u32 regs_buff[ATL2_REGS_LEN]; */
|
||||
u32 pci_state[16];
|
||||
|
||||
u32 *config_space;
|
||||
};
|
||||
|
||||
enum atl2_state_t {
|
||||
__ATL2_TESTING,
|
||||
__ATL2_RESETTING,
|
||||
__ATL2_DOWN
|
||||
};
|
||||
|
||||
#endif /* _ATL2_H_ */
|
||||
269
drivers/net/ethernet/atheros/atlx/atlx.c
Normal file
269
drivers/net/ethernet/atheros/atlx/atlx.c
Normal file
@@ -0,0 +1,269 @@
|
||||
/* atlx.c -- common functions for Attansic network drivers
|
||||
*
|
||||
* Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
|
||||
* Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
|
||||
* Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
|
||||
* Copyright(c) 2007 Atheros Corporation. All rights reserved.
|
||||
*
|
||||
* Derived from Intel e1000 driver
|
||||
* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59
|
||||
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
/* Including this file like a header is a temporary hack, I promise. -- CHS */
|
||||
#ifndef ATLX_C
|
||||
#define ATLX_C
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/if.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/socket.h>
|
||||
#include <linux/sockios.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/workqueue.h>
|
||||
|
||||
#include "atlx.h"
|
||||
|
||||
static s32 atlx_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data);
|
||||
static u32 atlx_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr);
|
||||
static void atlx_set_mac_addr(struct atl1_hw *hw);
|
||||
|
||||
static struct atlx_spi_flash_dev flash_table[] = {
|
||||
/* MFR_NAME WRSR READ PRGM WREN WRDI RDSR RDID SEC_ERS CHIP_ERS */
|
||||
{"Atmel", 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62},
|
||||
{"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60},
|
||||
{"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7},
|
||||
};
|
||||
|
||||
static int atlx_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
|
||||
{
|
||||
switch (cmd) {
|
||||
case SIOCGMIIPHY:
|
||||
case SIOCGMIIREG:
|
||||
case SIOCSMIIREG:
|
||||
return atlx_mii_ioctl(netdev, ifr, cmd);
|
||||
default:
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* atlx_set_mac - Change the Ethernet Address of the NIC
|
||||
* @netdev: network interface device structure
|
||||
* @p: pointer to an address structure
|
||||
*
|
||||
* Returns 0 on success, negative on failure
|
||||
*/
|
||||
static int atlx_set_mac(struct net_device *netdev, void *p)
|
||||
{
|
||||
struct atlx_adapter *adapter = netdev_priv(netdev);
|
||||
struct sockaddr *addr = p;
|
||||
|
||||
if (netif_running(netdev))
|
||||
return -EBUSY;
|
||||
|
||||
if (!is_valid_ether_addr(addr->sa_data))
|
||||
return -EADDRNOTAVAIL;
|
||||
|
||||
memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
|
||||
memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
|
||||
|
||||
atlx_set_mac_addr(&adapter->hw);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void atlx_check_for_link(struct atlx_adapter *adapter)
|
||||
{
|
||||
struct net_device *netdev = adapter->netdev;
|
||||
u16 phy_data = 0;
|
||||
|
||||
spin_lock(&adapter->lock);
|
||||
adapter->phy_timer_pending = false;
|
||||
atlx_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
|
||||
atlx_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
|
||||
spin_unlock(&adapter->lock);
|
||||
|
||||
/* notify upper layer link down ASAP */
|
||||
if (!(phy_data & BMSR_LSTATUS)) {
|
||||
/* Link Down */
|
||||
if (netif_carrier_ok(netdev)) {
|
||||
/* old link state: Up */
|
||||
dev_info(&adapter->pdev->dev, "%s link is down\n",
|
||||
netdev->name);
|
||||
adapter->link_speed = SPEED_0;
|
||||
netif_carrier_off(netdev);
|
||||
}
|
||||
}
|
||||
schedule_work(&adapter->link_chg_task);
|
||||
}
|
||||
|
||||
/*
|
||||
* atlx_set_multi - Multicast and Promiscuous mode set
|
||||
* @netdev: network interface device structure
|
||||
*
|
||||
* The set_multi entry point is called whenever the multicast address
|
||||
* list or the network interface flags are updated. This routine is
|
||||
* responsible for configuring the hardware for proper multicast,
|
||||
* promiscuous mode, and all-multi behavior.
|
||||
*/
|
||||
static void atlx_set_multi(struct net_device *netdev)
|
||||
{
|
||||
struct atlx_adapter *adapter = netdev_priv(netdev);
|
||||
struct atlx_hw *hw = &adapter->hw;
|
||||
struct netdev_hw_addr *ha;
|
||||
u32 rctl;
|
||||
u32 hash_value;
|
||||
|
||||
/* Check for Promiscuous and All Multicast modes */
|
||||
rctl = ioread32(hw->hw_addr + REG_MAC_CTRL);
|
||||
if (netdev->flags & IFF_PROMISC)
|
||||
rctl |= MAC_CTRL_PROMIS_EN;
|
||||
else if (netdev->flags & IFF_ALLMULTI) {
|
||||
rctl |= MAC_CTRL_MC_ALL_EN;
|
||||
rctl &= ~MAC_CTRL_PROMIS_EN;
|
||||
} else
|
||||
rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
|
||||
|
||||
iowrite32(rctl, hw->hw_addr + REG_MAC_CTRL);
|
||||
|
||||
/* clear the old settings from the multicast hash table */
|
||||
iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
|
||||
iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
|
||||
|
||||
/* compute mc addresses' hash value ,and put it into hash table */
|
||||
netdev_for_each_mc_addr(ha, netdev) {
|
||||
hash_value = atlx_hash_mc_addr(hw, ha->addr);
|
||||
atlx_hash_set(hw, hash_value);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* atlx_irq_enable - Enable default interrupt generation settings
|
||||
* @adapter: board private structure
|
||||
*/
|
||||
static void atlx_irq_enable(struct atlx_adapter *adapter)
|
||||
{
|
||||
iowrite32(IMR_NORMAL_MASK, adapter->hw.hw_addr + REG_IMR);
|
||||
ioread32(adapter->hw.hw_addr + REG_IMR);
|
||||
}
|
||||
|
||||
/*
|
||||
* atlx_irq_disable - Mask off interrupt generation on the NIC
|
||||
* @adapter: board private structure
|
||||
*/
|
||||
static void atlx_irq_disable(struct atlx_adapter *adapter)
|
||||
{
|
||||
iowrite32(0, adapter->hw.hw_addr + REG_IMR);
|
||||
ioread32(adapter->hw.hw_addr + REG_IMR);
|
||||
synchronize_irq(adapter->pdev->irq);
|
||||
}
|
||||
|
||||
static void atlx_clear_phy_int(struct atlx_adapter *adapter)
|
||||
{
|
||||
u16 phy_data;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&adapter->lock, flags);
|
||||
atlx_read_phy_reg(&adapter->hw, 19, &phy_data);
|
||||
spin_unlock_irqrestore(&adapter->lock, flags);
|
||||
}
|
||||
|
||||
/*
|
||||
* atlx_tx_timeout - Respond to a Tx Hang
|
||||
* @netdev: network interface device structure
|
||||
*/
|
||||
static void atlx_tx_timeout(struct net_device *netdev)
|
||||
{
|
||||
struct atlx_adapter *adapter = netdev_priv(netdev);
|
||||
/* Do the reset outside of interrupt context */
|
||||
schedule_work(&adapter->tx_timeout_task);
|
||||
}
|
||||
|
||||
/*
|
||||
* atlx_link_chg_task - deal with link change event Out of interrupt context
|
||||
*/
|
||||
static void atlx_link_chg_task(struct work_struct *work)
|
||||
{
|
||||
struct atlx_adapter *adapter;
|
||||
unsigned long flags;
|
||||
|
||||
adapter = container_of(work, struct atlx_adapter, link_chg_task);
|
||||
|
||||
spin_lock_irqsave(&adapter->lock, flags);
|
||||
atlx_check_link(adapter);
|
||||
spin_unlock_irqrestore(&adapter->lock, flags);
|
||||
}
|
||||
|
||||
static void __atlx_vlan_mode(u32 features, u32 *ctrl)
|
||||
{
|
||||
if (features & NETIF_F_HW_VLAN_RX) {
|
||||
/* enable VLAN tag insert/strip */
|
||||
*ctrl |= MAC_CTRL_RMV_VLAN;
|
||||
} else {
|
||||
/* disable VLAN tag insert/strip */
|
||||
*ctrl &= ~MAC_CTRL_RMV_VLAN;
|
||||
}
|
||||
}
|
||||
|
||||
static void atlx_vlan_mode(struct net_device *netdev, u32 features)
|
||||
{
|
||||
struct atlx_adapter *adapter = netdev_priv(netdev);
|
||||
unsigned long flags;
|
||||
u32 ctrl;
|
||||
|
||||
spin_lock_irqsave(&adapter->lock, flags);
|
||||
/* atlx_irq_disable(adapter); FIXME: confirm/remove */
|
||||
ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
|
||||
__atlx_vlan_mode(features, &ctrl);
|
||||
iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
|
||||
/* atlx_irq_enable(adapter); FIXME */
|
||||
spin_unlock_irqrestore(&adapter->lock, flags);
|
||||
}
|
||||
|
||||
static void atlx_restore_vlan(struct atlx_adapter *adapter)
|
||||
{
|
||||
atlx_vlan_mode(adapter->netdev, adapter->netdev->features);
|
||||
}
|
||||
|
||||
static u32 atlx_fix_features(struct net_device *netdev, u32 features)
|
||||
{
|
||||
/*
|
||||
* Since there is no support for separate rx/tx vlan accel
|
||||
* enable/disable make sure tx flag is always in same state as rx.
|
||||
*/
|
||||
if (features & NETIF_F_HW_VLAN_RX)
|
||||
features |= NETIF_F_HW_VLAN_TX;
|
||||
else
|
||||
features &= ~NETIF_F_HW_VLAN_TX;
|
||||
|
||||
return features;
|
||||
}
|
||||
|
||||
static int atlx_set_features(struct net_device *netdev, u32 features)
|
||||
{
|
||||
u32 changed = netdev->features ^ features;
|
||||
|
||||
if (changed & NETIF_F_HW_VLAN_RX)
|
||||
atlx_vlan_mode(netdev, features);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* ATLX_C */
|
||||
503
drivers/net/ethernet/atheros/atlx/atlx.h
Normal file
503
drivers/net/ethernet/atheros/atlx/atlx.h
Normal file
@@ -0,0 +1,503 @@
|
||||
/* atlx_hw.h -- common hardware definitions for Attansic network drivers
|
||||
*
|
||||
* Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
|
||||
* Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
|
||||
* Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
|
||||
* Copyright(c) 2007 Atheros Corporation. All rights reserved.
|
||||
*
|
||||
* Derived from Intel e1000 driver
|
||||
* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59
|
||||
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef ATLX_H
|
||||
#define ATLX_H
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#define ATLX_ERR_PHY 2
|
||||
#define ATLX_ERR_PHY_SPEED 7
|
||||
#define ATLX_ERR_PHY_RES 8
|
||||
|
||||
#define SPEED_0 0xffff
|
||||
#define SPEED_10 10
|
||||
#define SPEED_100 100
|
||||
#define SPEED_1000 1000
|
||||
#define HALF_DUPLEX 1
|
||||
#define FULL_DUPLEX 2
|
||||
|
||||
#define MEDIA_TYPE_AUTO_SENSOR 0
|
||||
|
||||
/* register definitions */
|
||||
#define REG_PM_CTRLSTAT 0x44
|
||||
|
||||
#define REG_PCIE_CAP_LIST 0x58
|
||||
|
||||
#define REG_VPD_CAP 0x6C
|
||||
#define VPD_CAP_ID_MASK 0xFF
|
||||
#define VPD_CAP_ID_SHIFT 0
|
||||
#define VPD_CAP_NEXT_PTR_MASK 0xFF
|
||||
#define VPD_CAP_NEXT_PTR_SHIFT 8
|
||||
#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
|
||||
#define VPD_CAP_VPD_ADDR_SHIFT 16
|
||||
#define VPD_CAP_VPD_FLAG 0x80000000
|
||||
|
||||
#define REG_VPD_DATA 0x70
|
||||
|
||||
#define REG_SPI_FLASH_CTRL 0x200
|
||||
#define SPI_FLASH_CTRL_STS_NON_RDY 0x1
|
||||
#define SPI_FLASH_CTRL_STS_WEN 0x2
|
||||
#define SPI_FLASH_CTRL_STS_WPEN 0x80
|
||||
#define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF
|
||||
#define SPI_FLASH_CTRL_DEV_STS_SHIFT 0
|
||||
#define SPI_FLASH_CTRL_INS_MASK 0x7
|
||||
#define SPI_FLASH_CTRL_INS_SHIFT 8
|
||||
#define SPI_FLASH_CTRL_START 0x800
|
||||
#define SPI_FLASH_CTRL_EN_VPD 0x2000
|
||||
#define SPI_FLASH_CTRL_LDSTART 0x8000
|
||||
#define SPI_FLASH_CTRL_CS_HI_MASK 0x3
|
||||
#define SPI_FLASH_CTRL_CS_HI_SHIFT 16
|
||||
#define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3
|
||||
#define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18
|
||||
#define SPI_FLASH_CTRL_CLK_LO_MASK 0x3
|
||||
#define SPI_FLASH_CTRL_CLK_LO_SHIFT 20
|
||||
#define SPI_FLASH_CTRL_CLK_HI_MASK 0x3
|
||||
#define SPI_FLASH_CTRL_CLK_HI_SHIFT 22
|
||||
#define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3
|
||||
#define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24
|
||||
#define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3
|
||||
#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26
|
||||
#define SPI_FLASH_CTRL_WAIT_READY 0x10000000
|
||||
|
||||
#define REG_SPI_ADDR 0x204
|
||||
|
||||
#define REG_SPI_DATA 0x208
|
||||
|
||||
#define REG_SPI_FLASH_CONFIG 0x20C
|
||||
#define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF
|
||||
#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0
|
||||
#define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3
|
||||
#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24
|
||||
#define SPI_FLASH_CONFIG_LD_EXIST 0x4000000
|
||||
|
||||
#define REG_SPI_FLASH_OP_PROGRAM 0x210
|
||||
#define REG_SPI_FLASH_OP_SC_ERASE 0x211
|
||||
#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212
|
||||
#define REG_SPI_FLASH_OP_RDID 0x213
|
||||
#define REG_SPI_FLASH_OP_WREN 0x214
|
||||
#define REG_SPI_FLASH_OP_RDSR 0x215
|
||||
#define REG_SPI_FLASH_OP_WRSR 0x216
|
||||
#define REG_SPI_FLASH_OP_READ 0x217
|
||||
|
||||
#define REG_TWSI_CTRL 0x218
|
||||
#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
|
||||
#define TWSI_CTRL_LD_OFFSET_SHIFT 0
|
||||
#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
|
||||
#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
|
||||
#define TWSI_CTRL_SW_LDSTART 0x800
|
||||
#define TWSI_CTRL_HW_LDSTART 0x1000
|
||||
#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F
|
||||
#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
|
||||
#define TWSI_CTRL_LD_EXIST 0x400000
|
||||
#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
|
||||
#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
|
||||
#define TWSI_CTRL_FREQ_SEL_100K 0
|
||||
#define TWSI_CTRL_FREQ_SEL_200K 1
|
||||
#define TWSI_CTRL_FREQ_SEL_300K 2
|
||||
#define TWSI_CTRL_FREQ_SEL_400K 3
|
||||
#define TWSI_CTRL_SMB_SLV_ADDR /* FIXME: define or remove */
|
||||
#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
|
||||
#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
|
||||
|
||||
#define REG_PCIE_DEV_MISC_CTRL 0x21C
|
||||
#define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2
|
||||
#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1
|
||||
#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4
|
||||
#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8
|
||||
#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10
|
||||
|
||||
#define REG_PCIE_PHYMISC 0x1000
|
||||
#define PCIE_PHYMISC_FORCE_RCV_DET 0x4
|
||||
|
||||
#define REG_PCIE_DLL_TX_CTRL1 0x1104
|
||||
#define PCIE_DLL_TX_CTRL1_SEL_NOR_CLK 0x400
|
||||
#define PCIE_DLL_TX_CTRL1_DEF 0x568
|
||||
|
||||
#define REG_LTSSM_TEST_MODE 0x12FC
|
||||
#define LTSSM_TEST_MODE_DEF 0x6500
|
||||
|
||||
/* Master Control Register */
|
||||
#define REG_MASTER_CTRL 0x1400
|
||||
#define MASTER_CTRL_SOFT_RST 0x1
|
||||
#define MASTER_CTRL_MTIMER_EN 0x2
|
||||
#define MASTER_CTRL_ITIMER_EN 0x4
|
||||
#define MASTER_CTRL_MANUAL_INT 0x8
|
||||
#define MASTER_CTRL_REV_NUM_SHIFT 16
|
||||
#define MASTER_CTRL_REV_NUM_MASK 0xFF
|
||||
#define MASTER_CTRL_DEV_ID_SHIFT 24
|
||||
#define MASTER_CTRL_DEV_ID_MASK 0xFF
|
||||
|
||||
/* Timer Initial Value Register */
|
||||
#define REG_MANUAL_TIMER_INIT 0x1404
|
||||
|
||||
/* IRQ Moderator Timer Initial Value Register */
|
||||
#define REG_IRQ_MODU_TIMER_INIT 0x1408
|
||||
|
||||
#define REG_PHY_ENABLE 0x140C
|
||||
|
||||
/* IRQ Anti-Lost Timer Initial Value Register */
|
||||
#define REG_CMBDISDMA_TIMER 0x140E
|
||||
|
||||
/* Block IDLE Status Register */
|
||||
#define REG_IDLE_STATUS 0x1410
|
||||
|
||||
/* MDIO Control Register */
|
||||
#define REG_MDIO_CTRL 0x1414
|
||||
#define MDIO_DATA_MASK 0xFFFF
|
||||
#define MDIO_DATA_SHIFT 0
|
||||
#define MDIO_REG_ADDR_MASK 0x1F
|
||||
#define MDIO_REG_ADDR_SHIFT 16
|
||||
#define MDIO_RW 0x200000
|
||||
#define MDIO_SUP_PREAMBLE 0x400000
|
||||
#define MDIO_START 0x800000
|
||||
#define MDIO_CLK_SEL_SHIFT 24
|
||||
#define MDIO_CLK_25_4 0
|
||||
#define MDIO_CLK_25_6 2
|
||||
#define MDIO_CLK_25_8 3
|
||||
#define MDIO_CLK_25_10 4
|
||||
#define MDIO_CLK_25_14 5
|
||||
#define MDIO_CLK_25_20 6
|
||||
#define MDIO_CLK_25_28 7
|
||||
#define MDIO_BUSY 0x8000000
|
||||
|
||||
/* MII PHY Status Register */
|
||||
#define REG_PHY_STATUS 0x1418
|
||||
|
||||
/* BIST Control and Status Register0 (for the Packet Memory) */
|
||||
#define REG_BIST0_CTRL 0x141C
|
||||
#define BIST0_NOW 0x1
|
||||
#define BIST0_SRAM_FAIL 0x2
|
||||
#define BIST0_FUSE_FLAG 0x4
|
||||
#define REG_BIST1_CTRL 0x1420
|
||||
#define BIST1_NOW 0x1
|
||||
#define BIST1_SRAM_FAIL 0x2
|
||||
#define BIST1_FUSE_FLAG 0x4
|
||||
|
||||
/* SerDes Lock Detect Control and Status Register */
|
||||
#define REG_SERDES_LOCK 0x1424
|
||||
#define SERDES_LOCK_DETECT 1
|
||||
#define SERDES_LOCK_DETECT_EN 2
|
||||
|
||||
/* MAC Control Register */
|
||||
#define REG_MAC_CTRL 0x1480
|
||||
#define MAC_CTRL_TX_EN 1
|
||||
#define MAC_CTRL_RX_EN 2
|
||||
#define MAC_CTRL_TX_FLOW 4
|
||||
#define MAC_CTRL_RX_FLOW 8
|
||||
#define MAC_CTRL_LOOPBACK 0x10
|
||||
#define MAC_CTRL_DUPLX 0x20
|
||||
#define MAC_CTRL_ADD_CRC 0x40
|
||||
#define MAC_CTRL_PAD 0x80
|
||||
#define MAC_CTRL_LENCHK 0x100
|
||||
#define MAC_CTRL_HUGE_EN 0x200
|
||||
#define MAC_CTRL_PRMLEN_SHIFT 10
|
||||
#define MAC_CTRL_PRMLEN_MASK 0xF
|
||||
#define MAC_CTRL_RMV_VLAN 0x4000
|
||||
#define MAC_CTRL_PROMIS_EN 0x8000
|
||||
#define MAC_CTRL_MC_ALL_EN 0x2000000
|
||||
#define MAC_CTRL_BC_EN 0x4000000
|
||||
|
||||
/* MAC IPG/IFG Control Register */
|
||||
#define REG_MAC_IPG_IFG 0x1484
|
||||
#define MAC_IPG_IFG_IPGT_SHIFT 0
|
||||
#define MAC_IPG_IFG_IPGT_MASK 0x7F
|
||||
#define MAC_IPG_IFG_MIFG_SHIFT 8
|
||||
#define MAC_IPG_IFG_MIFG_MASK 0xFF
|
||||
#define MAC_IPG_IFG_IPGR1_SHIFT 16
|
||||
#define MAC_IPG_IFG_IPGR1_MASK 0x7F
|
||||
#define MAC_IPG_IFG_IPGR2_SHIFT 24
|
||||
#define MAC_IPG_IFG_IPGR2_MASK 0x7F
|
||||
|
||||
/* MAC STATION ADDRESS */
|
||||
#define REG_MAC_STA_ADDR 0x1488
|
||||
|
||||
/* Hash table for multicast address */
|
||||
#define REG_RX_HASH_TABLE 0x1490
|
||||
|
||||
/* MAC Half-Duplex Control Register */
|
||||
#define REG_MAC_HALF_DUPLX_CTRL 0x1498
|
||||
#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0
|
||||
#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3FF
|
||||
#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12
|
||||
#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xF
|
||||
#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000
|
||||
#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000
|
||||
#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000
|
||||
#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000
|
||||
#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20
|
||||
#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xF
|
||||
#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24
|
||||
#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xF
|
||||
|
||||
/* Maximum Frame Length Control Register */
|
||||
#define REG_MTU 0x149C
|
||||
|
||||
/* Wake-On-Lan control register */
|
||||
#define REG_WOL_CTRL 0x14A0
|
||||
#define WOL_PATTERN_EN 0x1
|
||||
#define WOL_PATTERN_PME_EN 0x2
|
||||
#define WOL_MAGIC_EN 0x4
|
||||
#define WOL_MAGIC_PME_EN 0x8
|
||||
#define WOL_LINK_CHG_EN 0x10
|
||||
#define WOL_LINK_CHG_PME_EN 0x20
|
||||
#define WOL_PATTERN_ST 0x100
|
||||
#define WOL_MAGIC_ST 0x200
|
||||
#define WOL_LINKCHG_ST 0x400
|
||||
#define WOL_PT0_EN 0x10000
|
||||
#define WOL_PT1_EN 0x20000
|
||||
#define WOL_PT2_EN 0x40000
|
||||
#define WOL_PT3_EN 0x80000
|
||||
#define WOL_PT4_EN 0x100000
|
||||
#define WOL_PT0_MATCH 0x1000000
|
||||
#define WOL_PT1_MATCH 0x2000000
|
||||
#define WOL_PT2_MATCH 0x4000000
|
||||
#define WOL_PT3_MATCH 0x8000000
|
||||
#define WOL_PT4_MATCH 0x10000000
|
||||
|
||||
/* Internal SRAM Partition Register, high 32 bits */
|
||||
#define REG_SRAM_RFD_ADDR 0x1500
|
||||
|
||||
/* Descriptor Control register, high 32 bits */
|
||||
#define REG_DESC_BASE_ADDR_HI 0x1540
|
||||
|
||||
/* Interrupt Status Register */
|
||||
#define REG_ISR 0x1600
|
||||
#define ISR_UR_DETECTED 0x1000000
|
||||
#define ISR_FERR_DETECTED 0x2000000
|
||||
#define ISR_NFERR_DETECTED 0x4000000
|
||||
#define ISR_CERR_DETECTED 0x8000000
|
||||
#define ISR_PHY_LINKDOWN 0x10000000
|
||||
#define ISR_DIS_INT 0x80000000
|
||||
|
||||
/* Interrupt Mask Register */
|
||||
#define REG_IMR 0x1604
|
||||
|
||||
#define REG_RFD_RRD_IDX 0x1800
|
||||
#define REG_TPD_IDX 0x1804
|
||||
|
||||
/* MII definitions */
|
||||
|
||||
/* PHY Common Register */
|
||||
#define MII_ATLX_CR 0x09
|
||||
#define MII_ATLX_SR 0x0A
|
||||
#define MII_ATLX_ESR 0x0F
|
||||
#define MII_ATLX_PSCR 0x10
|
||||
#define MII_ATLX_PSSR 0x11
|
||||
|
||||
/* PHY Control Register */
|
||||
#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100,
|
||||
* 00=10
|
||||
*/
|
||||
#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
|
||||
#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
|
||||
#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
|
||||
#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
|
||||
#define MII_CR_POWER_DOWN 0x0800 /* Power down */
|
||||
#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
|
||||
#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100,
|
||||
* 00=10
|
||||
*/
|
||||
#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
|
||||
#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
|
||||
#define MII_CR_SPEED_MASK 0x2040
|
||||
#define MII_CR_SPEED_1000 0x0040
|
||||
#define MII_CR_SPEED_100 0x2000
|
||||
#define MII_CR_SPEED_10 0x0000
|
||||
|
||||
/* PHY Status Register */
|
||||
#define MII_SR_EXTENDED_CAPS 0x0001 /* Ext register capabilities */
|
||||
#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
|
||||
#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
|
||||
#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
|
||||
#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
|
||||
#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
|
||||
#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
|
||||
#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext stat info in Reg 0x0F */
|
||||
#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
|
||||
#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
|
||||
#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
|
||||
#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
|
||||
#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
|
||||
#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
|
||||
#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
|
||||
|
||||
/* Link partner ability register */
|
||||
#define MII_LPA_SLCT 0x001f /* Same as advertise selector */
|
||||
#define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
|
||||
#define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
|
||||
#define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
|
||||
#define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
|
||||
#define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */
|
||||
#define MII_LPA_PAUSE 0x0400 /* PAUSE */
|
||||
#define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */
|
||||
#define MII_LPA_RFAULT 0x2000 /* Link partner faulted */
|
||||
#define MII_LPA_LPACK 0x4000 /* Link partner acked us */
|
||||
#define MII_LPA_NPAGE 0x8000 /* Next page bit */
|
||||
|
||||
/* Autoneg Advertisement Register */
|
||||
#define MII_AR_SELECTOR_FIELD 0x0001 /* IEEE 802.3 CSMA/CD */
|
||||
#define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
|
||||
#define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
|
||||
#define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
|
||||
#define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
|
||||
#define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
|
||||
#define MII_AR_PAUSE 0x0400 /* Pause operation desired */
|
||||
#define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Dir bit */
|
||||
#define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
|
||||
#define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability support */
|
||||
#define MII_AR_SPEED_MASK 0x01E0
|
||||
#define MII_AR_DEFAULT_CAP_MASK 0x0DE0
|
||||
|
||||
/* 1000BASE-T Control Register */
|
||||
#define MII_ATLX_CR_1000T_HD_CAPS 0x0100 /* Adv 1000T HD cap */
|
||||
#define MII_ATLX_CR_1000T_FD_CAPS 0x0200 /* Adv 1000T FD cap */
|
||||
#define MII_ATLX_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device,
|
||||
* 0=DTE device */
|
||||
#define MII_ATLX_CR_1000T_MS_VALUE 0x0800 /* 1=Config PHY as Master,
|
||||
* 0=Configure PHY as Slave */
|
||||
#define MII_ATLX_CR_1000T_MS_ENABLE 0x1000 /* 1=Man Master/Slave config,
|
||||
* 0=Auto Master/Slave config
|
||||
*/
|
||||
#define MII_ATLX_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
|
||||
#define MII_ATLX_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
|
||||
#define MII_ATLX_CR_1000T_TEST_MODE_2 0x4000 /* Master Xmit Jitter test */
|
||||
#define MII_ATLX_CR_1000T_TEST_MODE_3 0x6000 /* Slave Xmit Jitter test */
|
||||
#define MII_ATLX_CR_1000T_TEST_MODE_4 0x8000 /* Xmitter Distortion test */
|
||||
#define MII_ATLX_CR_1000T_SPEED_MASK 0x0300
|
||||
#define MII_ATLX_CR_1000T_DEFAULT_CAP_MASK 0x0300
|
||||
|
||||
/* 1000BASE-T Status Register */
|
||||
#define MII_ATLX_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
|
||||
#define MII_ATLX_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
|
||||
#define MII_ATLX_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
|
||||
#define MII_ATLX_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
|
||||
#define MII_ATLX_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master
|
||||
* 0=Slave
|
||||
*/
|
||||
#define MII_ATLX_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config
|
||||
* fault */
|
||||
#define MII_ATLX_SR_1000T_REMOTE_RX_STATUS_SHIFT 12
|
||||
#define MII_ATLX_SR_1000T_LOCAL_RX_STATUS_SHIFT 13
|
||||
|
||||
/* Extended Status Register */
|
||||
#define MII_ATLX_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
|
||||
#define MII_ATLX_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
|
||||
#define MII_ATLX_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
|
||||
#define MII_ATLX_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
|
||||
|
||||
/* ATLX PHY Specific Control Register */
|
||||
#define MII_ATLX_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Func disabled */
|
||||
#define MII_ATLX_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enbld */
|
||||
#define MII_ATLX_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
|
||||
#define MII_ATLX_PSCR_MAC_POWERDOWN 0x0008
|
||||
#define MII_ATLX_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low
|
||||
* 0=CLK125 toggling
|
||||
*/
|
||||
#define MII_ATLX_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5,
|
||||
* Manual MDI configuration
|
||||
*/
|
||||
#define MII_ATLX_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
|
||||
#define MII_ATLX_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover
|
||||
* 100BASE-TX/10BASE-T: MDI
|
||||
* Mode */
|
||||
#define MII_ATLX_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
|
||||
* all speeds.
|
||||
*/
|
||||
#define MII_ATLX_PSCR_10BT_EXT_DIST_ENABLE 0x0080 /* 1=Enable Extended
|
||||
* 10BASE-T distance
|
||||
* (Lower 10BASE-T RX
|
||||
* Threshold)
|
||||
* 0=Normal 10BASE-T RX
|
||||
* Threshold
|
||||
*/
|
||||
#define MII_ATLX_PSCR_MII_5BIT_ENABLE 0x0100 /* 1=5-Bit interface in
|
||||
* 100BASE-TX
|
||||
* 0=MII interface in
|
||||
* 100BASE-TX
|
||||
*/
|
||||
#define MII_ATLX_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler dsbl */
|
||||
#define MII_ATLX_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
|
||||
#define MII_ATLX_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
|
||||
#define MII_ATLX_PSCR_POLARITY_REVERSAL_SHIFT 1
|
||||
#define MII_ATLX_PSCR_AUTO_X_MODE_SHIFT 5
|
||||
#define MII_ATLX_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
|
||||
|
||||
/* ATLX PHY Specific Status Register */
|
||||
#define MII_ATLX_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
|
||||
#define MII_ATLX_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
|
||||
#define MII_ATLX_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
|
||||
#define MII_ATLX_PSSR_10MBS 0x0000 /* 00=10Mbs */
|
||||
#define MII_ATLX_PSSR_100MBS 0x4000 /* 01=100Mbs */
|
||||
#define MII_ATLX_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
|
||||
|
||||
#define MII_DBG_ADDR 0x1D
|
||||
#define MII_DBG_DATA 0x1E
|
||||
|
||||
/* PCI Command Register Bit Definitions */
|
||||
#define PCI_REG_COMMAND 0x04 /* PCI Command Register */
|
||||
#define CMD_IO_SPACE 0x0001
|
||||
#define CMD_MEMORY_SPACE 0x0002
|
||||
#define CMD_BUS_MASTER 0x0004
|
||||
|
||||
/* Wake Up Filter Control */
|
||||
#define ATLX_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
|
||||
#define ATLX_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
|
||||
#define ATLX_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
|
||||
#define ATLX_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
|
||||
#define ATLX_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
|
||||
|
||||
#define ADVERTISE_10_HALF 0x0001
|
||||
#define ADVERTISE_10_FULL 0x0002
|
||||
#define ADVERTISE_100_HALF 0x0004
|
||||
#define ADVERTISE_100_FULL 0x0008
|
||||
#define ADVERTISE_1000_HALF 0x0010
|
||||
#define ADVERTISE_1000_FULL 0x0020
|
||||
#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */
|
||||
#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */
|
||||
|
||||
#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
|
||||
#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
|
||||
|
||||
/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA */
|
||||
#define EEPROM_SUM 0xBABA
|
||||
#define NODE_ADDRESS_SIZE 6
|
||||
|
||||
struct atlx_spi_flash_dev {
|
||||
const char *manu_name; /* manufacturer id */
|
||||
/* op-code */
|
||||
u8 cmd_wrsr;
|
||||
u8 cmd_read;
|
||||
u8 cmd_program;
|
||||
u8 cmd_wren;
|
||||
u8 cmd_wrdi;
|
||||
u8 cmd_rdsr;
|
||||
u8 cmd_rdid;
|
||||
u8 cmd_sector_erase;
|
||||
u8 cmd_chip_erase;
|
||||
};
|
||||
|
||||
#endif /* ATLX_H */
|
||||
Reference in New Issue
Block a user