drm/i915: Store the BIT(engine->id) as the engine's mask

In the next patch, we are introducing a broad virtual engine to encompass
multiple physical engines, losing the 1:1 nature of BIT(engine->id). To
reflect the broader set of engines implied by the virtual instance, lets
store the full bitmask.

v2: Use intel_engine_mask_t (s/ring_mask/engine_mask/)
v3: Tvrtko voted for moah churn so teach everyone to not mention ring
and use $class$instance throughout.
v4: Comment upon the disparity in bspec for using VCS1,VCS2 in gen8 and
VCS[0-4] in later gen. We opt to keep the code consistent and use
0-index naming throughout.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190305180332.30900-1-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
2019-03-05 18:03:30 +00:00
parent c8b502422b
commit 8a68d46436
45 changed files with 414 additions and 424 deletions

View File

@@ -10,12 +10,12 @@
#include <linux/seqlock.h>
#include "i915_gem_batch_pool.h"
#include "i915_reg.h"
#include "i915_pmu.h"
#include "i915_reg.h"
#include "i915_request.h"
#include "i915_selftest.h"
#include "i915_timeline.h"
#include "intel_device_info.h"
#include "intel_gpu_commands.h"
#include "intel_workarounds.h"
@@ -175,16 +175,16 @@ struct i915_request;
* Keep instances of the same type engine together.
*/
enum intel_engine_id {
RCS = 0,
BCS,
VCS,
RCS0 = 0,
BCS0,
VCS0,
VCS1,
VCS2,
VCS3,
VCS4,
#define _VCS(n) (VCS + (n))
VECS,
VECS2
#define _VECS(n) (VECS + (n))
#define _VCS(n) (VCS0 + (n))
VECS0,
VECS1
#define _VECS(n) (VECS0 + (n))
};
struct st_preempt_hang {
@@ -334,6 +334,7 @@ struct intel_engine_cs {
enum intel_engine_id id;
unsigned int hw_id;
unsigned int guc_id;
intel_engine_mask_t mask;
u8 uabi_class;
@@ -667,12 +668,6 @@ execlists_port_complete(struct intel_engine_execlists * const execlists,
return port;
}
static inline unsigned int
intel_engine_flag(const struct intel_engine_cs *engine)
{
return BIT(engine->id);
}
static inline u32
intel_read_status_page(const struct intel_engine_cs *engine, int reg)
{