Merge tag 'imx-dt-clkdep-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX device tree update with new clocks: - A series from Anson Huang to add i.MX8MN SoC and DDR4 EVK board device tree support. - Add DSP device tree support for i.MX8QXP SoC. * tag 'imx-dt-clkdep-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: imx8qxp: Add DSP DT node arm64: dts: imx8mn: Add cpu-freq support arm64: dts: imx8mn-ddr4-evk: Add rohm,bd71847 PMIC support arm64: dts: imx8mn-ddr4-evk: Add i2c1 support arm64: dts: freescale: Add i.MX8MN DDR4 EVK board support arm64: dts: imx8mn: Add gpio-ranges property arm64: dts: freescale: Add i.MX8MN dtsi support clk: imx8: Add DSP related clocks clk: imx: Add support for i.MX8MN clock driver clk: imx: Add API for clk unregister when driver probe fail clk: imx8mm: Make 1416X/1443X PLL macro definitions common for usage dt-bindings: imx: Add clock binding doc for i.MX8MN Link: https://lore.kernel.org/r/20190825153237.28829-4-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Этот коммит содержится в:
Arnd Bergmann
@@ -21,6 +21,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
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348
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
Обычный файл
348
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
Обычный файл
@@ -0,0 +1,348 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2019 NXP
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*/
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/dts-v1/;
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#include "imx8mn.dtsi"
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/ {
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model = "NXP i.MX8MNano DDR4 EVK board";
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compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn";
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chosen {
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stdout-path = &uart2;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&A53_0 {
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cpu-supply = <&buck2_reg>;
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
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MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
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MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
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MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
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MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
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MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
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MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
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MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
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MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
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MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
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MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
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MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
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MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
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MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
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MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
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>;
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};
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pinctrl_pmic: pmicirq {
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fsl,pins = <
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MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
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>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
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fsl,pins = <
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MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
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MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2grpgpio {
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fsl,pins = <
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MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
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MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
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MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
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MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
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MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
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MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
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MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
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fsl,pins = <
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MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
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MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
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MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
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MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
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MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
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MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
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MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
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fsl,pins = <
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MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
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MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
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MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
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MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
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MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
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MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
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MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
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MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
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MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
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MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
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MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
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MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
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MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
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MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
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MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
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MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
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MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
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>;
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};
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pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
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fsl,pins = <
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MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
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MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
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MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
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MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
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MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
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MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
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MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
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MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
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MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
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MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
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MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
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>;
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};
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pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
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fsl,pins = <
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MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
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MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
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MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
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MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
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MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
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MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
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MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
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MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
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MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
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MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
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MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
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>;
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};
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pinctrl_wdog: wdoggrp {
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fsl,pins = <
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MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
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>;
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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at803x,led-act-blind-workaround;
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at803x,eee-disabled;
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at803x,vddio-1p8v;
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};
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};
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pmic@4b {
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compatible = "rohm,bd71847";
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reg = <0x4b>;
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pinctrl-0 = <&pinctrl_pmic>;
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interrupt-parent = <&gpio1>;
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interrupts = <3 GPIO_ACTIVE_LOW>;
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rohm,reset-snvs-powered;
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regulators {
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buck1_reg: BUCK1 {
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regulator-name = "BUCK1";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <1250>;
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};
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|
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buck2_reg: BUCK2 {
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regulator-name = "BUCK2";
|
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regulator-min-microvolt = <700000>;
|
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regulator-max-microvolt = <1300000>;
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regulator-boot-on;
|
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regulator-always-on;
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regulator-ramp-delay = <1250>;
|
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};
|
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|
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buck3_reg: BUCK3 {
|
||||
// BUCK5 in datasheet
|
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regulator-name = "BUCK3";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
};
|
||||
|
||||
buck4_reg: BUCK4 {
|
||||
// BUCK6 in datasheet
|
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regulator-name = "BUCK4";
|
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regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
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regulator-always-on;
|
||||
};
|
||||
|
||||
buck5_reg: BUCK5 {
|
||||
// BUCK7 in datasheet
|
||||
regulator-name = "BUCK5";
|
||||
regulator-min-microvolt = <1605000>;
|
||||
regulator-max-microvolt = <1995000>;
|
||||
regulator-boot-on;
|
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regulator-always-on;
|
||||
};
|
||||
|
||||
buck6_reg: BUCK6 {
|
||||
// BUCK8 in datasheet
|
||||
regulator-name = "BUCK6";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: LDO1 {
|
||||
regulator-name = "LDO1";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: LDO2 {
|
||||
regulator-name = "LDO2";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: LDO3 {
|
||||
regulator-name = "LDO3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4_reg: LDO4 {
|
||||
regulator-name = "LDO4";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo6_reg: LDO6 {
|
||||
regulator-name = "LDO6";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&snvs_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 { /* console */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
758
arch/arm64/boot/dts/freescale/imx8mn.dtsi
Обычный файл
758
arch/arm64/boot/dts/freescale/imx8mn.dtsi
Обычный файл
@@ -0,0 +1,758 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx8mn-clock.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "imx8mn-pinfunc.h"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,imx8mn";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &fec1;
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
gpio3 = &gpio4;
|
||||
gpio4 = &gpio5;
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
i2c2 = &i2c3;
|
||||
i2c3 = &i2c4;
|
||||
mmc0 = &usdhc1;
|
||||
mmc1 = &usdhc2;
|
||||
mmc2 = &usdhc3;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
serial3 = &uart4;
|
||||
spi0 = &ecspi1;
|
||||
spi1 = &ecspi2;
|
||||
spi2 = &ecspi3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
A53_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0>;
|
||||
clock-latency = <61036>;
|
||||
clocks = <&clk IMX8MN_CLK_ARM>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
nvmem-cells = <&cpu_speed_grade>;
|
||||
nvmem-cell-names = "speed_grade";
|
||||
};
|
||||
|
||||
A53_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1>;
|
||||
clock-latency = <61036>;
|
||||
clocks = <&clk IMX8MN_CLK_ARM>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
};
|
||||
|
||||
A53_2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x2>;
|
||||
clock-latency = <61036>;
|
||||
clocks = <&clk IMX8MN_CLK_ARM>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
};
|
||||
|
||||
A53_3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x3>;
|
||||
clock-latency = <61036>;
|
||||
clocks = <&clk IMX8MN_CLK_ARM>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
};
|
||||
|
||||
A53_L2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
a53_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-1200000000 {
|
||||
opp-hz = /bits/ 64 <1200000000>;
|
||||
opp-microvolt = <850000>;
|
||||
opp-supported-hw = <0xb00>, <0x7>;
|
||||
clock-latency-ns = <150000>;
|
||||
opp-suspend;
|
||||
};
|
||||
|
||||
opp-1400000000 {
|
||||
opp-hz = /bits/ 64 <1400000000>;
|
||||
opp-microvolt = <950000>;
|
||||
opp-supported-hw = <0x300>, <0x7>;
|
||||
clock-latency-ns = <150000>;
|
||||
opp-suspend;
|
||||
};
|
||||
|
||||
opp-1500000000 {
|
||||
opp-hz = /bits/ 64 <1500000000>;
|
||||
opp-microvolt = <1000000>;
|
||||
opp-supported-hw = <0x100>, <0x3>;
|
||||
clock-latency-ns = <150000>;
|
||||
opp-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000 0 0x80000000>;
|
||||
};
|
||||
|
||||
osc_32k: clock-osc-32k {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "osc_32k";
|
||||
};
|
||||
|
||||
osc_24m: clock-osc-24m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "osc_24m";
|
||||
};
|
||||
|
||||
clk_ext1: clock-ext1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext1";
|
||||
};
|
||||
|
||||
clk_ext2: clock-ext2 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext2";
|
||||
};
|
||||
|
||||
clk_ext3: clock-ext3 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext3";
|
||||
};
|
||||
|
||||
clk_ext4: clock-ext4 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency= <133000000>;
|
||||
clock-output-names = "clk_ext4";
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
clock-frequency = <8000000>;
|
||||
arm,no-tick-in-suspend;
|
||||
};
|
||||
|
||||
soc@0 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x0 0x3e000000>;
|
||||
|
||||
aips1: bus@30000000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x30000000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
gpio1: gpio@30200000 {
|
||||
compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30200000 0x10000>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 10 30>;
|
||||
};
|
||||
|
||||
gpio2: gpio@30210000 {
|
||||
compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30210000 0x10000>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 40 21>;
|
||||
};
|
||||
|
||||
gpio3: gpio@30220000 {
|
||||
compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30220000 0x10000>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 61 26>;
|
||||
};
|
||||
|
||||
gpio4: gpio@30230000 {
|
||||
compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30230000 0x10000>;
|
||||
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 21 108 11>;
|
||||
};
|
||||
|
||||
gpio5: gpio@30240000 {
|
||||
compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30240000 0x10000>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 119 30>;
|
||||
};
|
||||
|
||||
wdog1: watchdog@30280000 {
|
||||
compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x30280000 0x10000>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog2: watchdog@30290000 {
|
||||
compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x30290000 0x10000>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog3: watchdog@302a0000 {
|
||||
compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x302a0000 0x10000>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdma3: dma-controller@302b0000 {
|
||||
compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
|
||||
reg = <0x302b0000 0x10000>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
|
||||
<&clk IMX8MN_CLK_SDMA3_ROOT>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
|
||||
};
|
||||
|
||||
sdma2: dma-controller@302c0000 {
|
||||
compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
|
||||
reg = <0x302c0000 0x10000>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
|
||||
<&clk IMX8MN_CLK_SDMA2_ROOT>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
|
||||
};
|
||||
|
||||
iomuxc: pinctrl@30330000 {
|
||||
compatible = "fsl,imx8mn-iomuxc";
|
||||
reg = <0x30330000 0x10000>;
|
||||
};
|
||||
|
||||
gpr: iomuxc-gpr@30340000 {
|
||||
compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
|
||||
reg = <0x30340000 0x10000>;
|
||||
};
|
||||
|
||||
ocotp: ocotp-ctrl@30350000 {
|
||||
compatible = "fsl,imx8mn-ocotp", "fsl,imx7d-ocotp", "syscon";
|
||||
reg = <0x30350000 0x10000>;
|
||||
clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpu_speed_grade: speed-grade@10 {
|
||||
reg = <0x10 4>;
|
||||
};
|
||||
};
|
||||
|
||||
anatop: anatop@30360000 {
|
||||
compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
|
||||
"syscon", "simple-bus";
|
||||
reg = <0x30360000 0x10000>;
|
||||
};
|
||||
|
||||
snvs: snvs@30370000 {
|
||||
compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
|
||||
reg = <0x30370000 0x10000>;
|
||||
|
||||
snvs_rtc: snvs-rtc-lp {
|
||||
compatible = "fsl,sec-v4.0-mon-rtc-lp";
|
||||
regmap = <&snvs>;
|
||||
offset = <0x34>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "snvs-rtc";
|
||||
};
|
||||
|
||||
snvs_pwrkey: snvs-powerkey {
|
||||
compatible = "fsl,sec-v4.0-pwrkey";
|
||||
regmap = <&snvs>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
linux,keycode = <KEY_POWER>;
|
||||
wakeup-source;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
clk: clock-controller@30380000 {
|
||||
compatible = "fsl,imx8mn-ccm";
|
||||
reg = <0x30380000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
|
||||
<&clk_ext3>, <&clk_ext4>;
|
||||
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
|
||||
"clk_ext3", "clk_ext4";
|
||||
};
|
||||
|
||||
src: reset-controller@30390000 {
|
||||
compatible = "fsl,imx8mn-src", "syscon";
|
||||
reg = <0x30390000 0x10000>;
|
||||
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
aips2: bus@30400000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x30400000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
pwm1: pwm@30660000 {
|
||||
compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x30660000 0x10000>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
|
||||
<&clk IMX8MN_CLK_PWM1_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2: pwm@30670000 {
|
||||
compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x30670000 0x10000>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
|
||||
<&clk IMX8MN_CLK_PWM2_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm3: pwm@30680000 {
|
||||
compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x30680000 0x10000>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
|
||||
<&clk IMX8MN_CLK_PWM3_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm4: pwm@30690000 {
|
||||
compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x30690000 0x10000>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
|
||||
<&clk IMX8MN_CLK_PWM4_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
aips3: bus@30800000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x30800000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
ecspi1: spi@30820000 {
|
||||
compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30820000 0x10000>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
|
||||
<&clk IMX8MN_CLK_ECSPI1_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi2: spi@30830000 {
|
||||
compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30830000 0x10000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
|
||||
<&clk IMX8MN_CLK_ECSPI2_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi3: spi@30840000 {
|
||||
compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30840000 0x10000>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
|
||||
<&clk IMX8MN_CLK_ECSPI3_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@30860000 {
|
||||
compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
|
||||
reg = <0x30860000 0x10000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
|
||||
<&clk IMX8MN_CLK_UART1_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@30880000 {
|
||||
compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
|
||||
reg = <0x30880000 0x10000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
|
||||
<&clk IMX8MN_CLK_UART3_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@30890000 {
|
||||
compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
|
||||
reg = <0x30890000 0x10000>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
|
||||
<&clk IMX8MN_CLK_UART2_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@30a20000 {
|
||||
compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30a20000 0x10000>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@30a30000 {
|
||||
compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30a30000 0x10000>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@30a40000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x30a40000 0x10000>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@30a50000 {
|
||||
compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30a50000 0x10000>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@30a60000 {
|
||||
compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
|
||||
reg = <0x30a60000 0x10000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
|
||||
<&clk IMX8MN_CLK_UART4_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc1: mmc@30b40000 {
|
||||
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b40000 0x10000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_DUMMY>,
|
||||
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MN_CLK_USDHC1_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
assigned-clocks = <&clk IMX8MN_CLK_USDHC1>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc2: mmc@30b50000 {
|
||||
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b50000 0x10000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_DUMMY>,
|
||||
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MN_CLK_USDHC2_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc3: mmc@30b60000 {
|
||||
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b60000 0x10000>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_DUMMY>,
|
||||
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MN_CLK_USDHC3_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdma1: dma-controller@30bd0000 {
|
||||
compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
|
||||
reg = <0x30bd0000 0x10000>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
|
||||
<&clk IMX8MN_CLK_SDMA1_ROOT>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
|
||||
};
|
||||
|
||||
fec1: ethernet@30be0000 {
|
||||
compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";
|
||||
reg = <0x30be0000 0x10000>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
|
||||
<&clk IMX8MN_CLK_ENET1_ROOT>,
|
||||
<&clk IMX8MN_CLK_ENET_TIMER>,
|
||||
<&clk IMX8MN_CLK_ENET_REF>,
|
||||
<&clk IMX8MN_CLK_ENET_PHY_REF>;
|
||||
clock-names = "ipg", "ahb", "ptp",
|
||||
"enet_clk_ref", "enet_out";
|
||||
assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
|
||||
<&clk IMX8MN_CLK_ENET_TIMER>,
|
||||
<&clk IMX8MN_CLK_ENET_REF>,
|
||||
<&clk IMX8MN_CLK_ENET_TIMER>;
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
|
||||
<&clk IMX8MN_SYS_PLL2_100M>,
|
||||
<&clk IMX8MN_SYS_PLL2_125M>;
|
||||
assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
|
||||
fsl,num-tx-queues = <3>;
|
||||
fsl,num-rx-queues = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
aips4: bus@32c00000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x32c00000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
usbotg1: usb@32e40000 {
|
||||
compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
|
||||
reg = <0x32e40000 0x200>;
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
|
||||
clock-names = "usb1_ctrl_root_clk";
|
||||
assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
|
||||
<&clk IMX8MN_CLK_USB_CORE_REF>;
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
|
||||
<&clk IMX8MN_SYS_PLL1_100M>;
|
||||
fsl,usbphy = <&usbphynop1>;
|
||||
fsl,usbmisc = <&usbmisc1 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbmisc1: usbmisc@32e40200 {
|
||||
compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
|
||||
#index-cells = <1>;
|
||||
reg = <0x32e40200 0x200>;
|
||||
};
|
||||
|
||||
usbotg2: usb@32e50000 {
|
||||
compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
|
||||
reg = <0x32e50000 0x200>;
|
||||
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
|
||||
clock-names = "usb1_ctrl_root_clk";
|
||||
assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
|
||||
<&clk IMX8MN_CLK_USB_CORE_REF>;
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
|
||||
<&clk IMX8MN_SYS_PLL1_100M>;
|
||||
fsl,usbphy = <&usbphynop2>;
|
||||
fsl,usbmisc = <&usbmisc2 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbmisc2: usbmisc@32e50200 {
|
||||
compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
|
||||
#index-cells = <1>;
|
||||
reg = <0x32e50200 0x200>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
dma_apbh: dma-controller@33000000 {
|
||||
compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
|
||||
reg = <0x33000000 0x2000>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <4>;
|
||||
clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
|
||||
};
|
||||
|
||||
gpmi: nand-controller@33002000 {
|
||||
compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
|
||||
reg-names = "gpmi-nand", "bch";
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "bch";
|
||||
clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
|
||||
<&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
|
||||
clock-names = "gpmi_io", "gpmi_bch_apb";
|
||||
dmas = <&dma_apbh 0>;
|
||||
dma-names = "rx-tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@38800000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0x38800000 0x10000>,
|
||||
<0x38880000 0xc0000>;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
usbphynop1: usbphynop1 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
|
||||
assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
|
||||
usbphynop2: usbphynop2 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
|
||||
assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
};
|
||||
@@ -230,3 +230,7 @@
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&adma_dsp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -113,6 +113,17 @@
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
dsp_reserved: dsp@92400000 {
|
||||
reg = <0 0x92400000 0 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@@ -204,6 +215,27 @@
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
adma_dsp: dsp@596e8000 {
|
||||
compatible = "fsl,imx8qxp-dsp";
|
||||
reg = <0x596e8000 0x88000>;
|
||||
clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
|
||||
<&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
|
||||
<&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
|
||||
clock-names = "ipg", "ocram", "core";
|
||||
power-domains = <&pd IMX_SC_R_MU_13A>,
|
||||
<&pd IMX_SC_R_MU_13B>,
|
||||
<&pd IMX_SC_R_DSP>,
|
||||
<&pd IMX_SC_R_DSP_RAM>;
|
||||
mbox-names = "txdb0", "txdb1",
|
||||
"rxdb0", "rxdb1";
|
||||
mboxes = <&lsio_mu13 2 0>,
|
||||
<&lsio_mu13 2 1>,
|
||||
<&lsio_mu13 3 0>,
|
||||
<&lsio_mu13 3 1>;
|
||||
memory-region = <&dsp_reserved>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
adma_lpuart0: serial@5a060000 {
|
||||
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
|
||||
reg = <0x5a060000 0x1000>;
|
||||
|
||||
Ссылка в новой задаче
Block a user