[MIPS] TXx9: Reorganize PCI code
Split out PCIC dependent code and SoC dependent code from board dependent code. Now TX4927 PCIC code is independent from TX4927/TX4938 SoC code. Also fix some build problems on CONFIG_PCI=n. As a bonus, "FPCIB0 Backplane Support" is available for all TX39/TX49 boards and PCI66 support is available for all TX49 boards. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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committed by
Ralf Baechle

parent
22b1d707ff
commit
89d63fe179
@@ -111,9 +111,6 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <asm/io.h>
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#ifdef CONFIG_TOSHIBA_FPCIB0
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#include <asm/i8259.h>
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#endif
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#include <asm/txx9/rbtx4927.h>
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#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0
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@@ -125,8 +122,6 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB
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#define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC
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#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2)
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extern int tx4927_using_backplane;
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static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
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static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
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@@ -146,17 +141,8 @@ int toshiba_rbtx4927_irq_nested(int sw_irq)
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u8 level3;
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level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
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if (level3) {
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if (level3)
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sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + fls(level3) - 1;
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#ifdef CONFIG_TOSHIBA_FPCIB0
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if (sw_irq == TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC &&
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tx4927_using_backplane) {
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int irq = i8259_irq();
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if (irq >= 0)
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sw_irq = irq;
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}
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#endif
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}
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return (sw_irq);
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}
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@@ -205,10 +191,6 @@ void __init arch_init_irq(void)
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tx4927_irq_init();
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toshiba_rbtx4927_irq_ioc_init();
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#ifdef CONFIG_TOSHIBA_FPCIB0
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if (tx4927_using_backplane)
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init_i8259_irqs();
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#endif
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/* Onboard 10M Ether: High Active */
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set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH);
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}
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