drm/meson: add mode selection limits against specific SoC revisions
The Amlogic S805X/Y uses the same die as the S905X, but with more limited graphics capabilities. This adds a soc version detection adding specific limitations on the HDMI mode selections. Here, we limit to HDMI 1.2a max HDMI PHY clock frequency. Changes sinces v1: - Moved frequency check in the vclk code, and also checks DMT modes Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [narmstrong: fixed commit message with HDMI 1.2a instead of HDMI 1.3a] Link: https://patchwork.freedesktop.org/patch/msgid/20200428092147.13698-1-narmstrong@baylibre.com
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@@ -725,6 +725,13 @@ meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq)
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/* In DMT mode, path after PLL is always /10 */
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freq *= 10;
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/* Check against soc revision/package limits */
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if (priv->limits) {
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if (priv->limits->max_hdmi_phy_freq &&
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freq > priv->limits->max_hdmi_phy_freq)
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return MODE_CLOCK_HIGH;
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}
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if (meson_hdmi_pll_find_params(priv, freq, &m, &frac, &od))
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return MODE_OK;
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@@ -762,7 +769,7 @@ static void meson_hdmi_pll_generic_set(struct meson_drm *priv,
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}
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enum drm_mode_status
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meson_vclk_vic_supported_freq(unsigned int phy_freq,
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meson_vclk_vic_supported_freq(struct meson_drm *priv, unsigned int phy_freq,
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unsigned int vclk_freq)
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{
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int i;
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@@ -770,6 +777,13 @@ meson_vclk_vic_supported_freq(unsigned int phy_freq,
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DRM_DEBUG_DRIVER("phy_freq = %d vclk_freq = %d\n",
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phy_freq, vclk_freq);
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/* Check against soc revision/package limits */
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if (priv->limits) {
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if (priv->limits->max_hdmi_phy_freq &&
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phy_freq > priv->limits->max_hdmi_phy_freq)
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return MODE_CLOCK_HIGH;
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}
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for (i = 0 ; params[i].pixel_freq ; ++i) {
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DRM_DEBUG_DRIVER("i = %d pixel_freq = %d alt = %d\n",
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i, params[i].pixel_freq,
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