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irqchip: keystone: Add irq controller ip driver

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On Keystone SOCs, DSP cores can send interrupts to ARM
host using the IRQ controller IP. It provides 28 IRQ
signals to ARM. The IRQ handler running on HOST OS can
identify DSP signal source by analyzing SRCCx bits in
IPCARx registers. This is one of the component used by
the IPC mechanism used on Keystone SOCs.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Link: https://lkml.kernel.org/r/1406126430-9978-1-git-send-email-grygorii.strashko@ti.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Grygorii Strashko
2014-07-23 17:40:30 +03:00
committed by Jason Cooper
parent 7d1311b93e
commit 89323f8c50
4 changed files with 276 additions and 0 deletions
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36
Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt Normal file
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Keystone 2 IRQ controller IP
On Keystone SOCs, DSP cores can send interrupts to ARM
host using the IRQ controller IP. It provides 28 IRQ signals to ARM.
The IRQ handler running on HOST OS can identify DSP signal source by
analyzing SRCCx bits in IPCARx registers. This is one of the component
used by the IPC mechanism used on Keystone SOCs.
Required Properties:
- compatible: should be "ti,keystone-irq"
- ti,syscon-dev : phandle and offset pair. The phandle to syscon used to
access device control registers and the offset inside
device control registers range.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode interrupt
source should be 1.
- interrupts: interrupt reference to primary interrupt controller
Please refer to interrupts.txt in this directory for details of the common
Interrupt Controllers bindings used by client devices.
Example:
kirq0: keystone_irq0@026202a0 {
compatible = "ti,keystone-irq";
ti,syscon-dev = <&devctrl 0x2a0>;
interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <1>;
};
dsp0: dsp0 {
compatible = "linux,rproc-user";
...
interrupt-parent = <&kirq0>;
interrupts = <10 2>;
};