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Merge tag 'mips_4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips

Browse Source 
Pull MIPS updates from James Hogan:
 "These are the main MIPS changes for 4.15.

  Fixes:
   - ralink: Fix MT7620 PCI build issues (4.5)
   - Disable cmpxchg64() and HAVE_VIRT_CPU_ACCOUNTING_GEN for 32-bit SMP
     (4.1)
   - Fix MIPS64 FP save/restore on 32-bit kernels (4.0)
   - ptrace: Pick up ptrace/seccomp changed syscall numbers (3.19)
   - ralink: Fix MT7628 pinmux (3.19)
   - BCM47XX: Fix LED inversion on WRT54GSv1 (3.17)
   - Fix n32 core dumping as o32 since regset support (3.13)
   - ralink: Drop obsolete USB_ARCH_HAS_HCD select

  Build system:
   - Default to "generic" (multiplatform) system type instead of IP22
   - Use generic little endian MIPS32 r2 configuration as default
     defconfig instead of ip22_defconfig

  FPU emulation:
   - Fix exception generation for certain R6 FPU instructions

  SMP:
   - Allow __cpu_number_map to be larger than NR_CPUS for sparse CPU id
     spaces

  Miscellaneous:
   - Add iomem resource for kernel bss section for kexec/kdump
   - Atomics: Nudge writes on bit unlock
   - DT files: Standardise "ok" -> "okay"

  Minor cleanups:
   - Define virt_to_pfn()
   - Make thread_saved_pc static
   - Simplify 32-bit sign extension in __read_64bit_c0_split()
   - DMA: Use vma_pages() helper
   - FPU emulation: Replace unsigned with unsigned int
   - MM: Removed unused lastpfn
   - Alchemy: Make clk_ops const
   - Lasat: Use setup_timer() helper
   - ralink: Use BIT() in MT7620 PCI driver

  Platform support:

  BMIPS:
  - Enable HARDIRQS_SW_RESEND

  Broadcom BCM63XX:
  - Add clkdev lookup support
  - Update clk driver, UART driver, DTs to handle named refclk from DTs
  - Split apart various clocks to more closely match hardware
  - Add ethernet clocks

  Cavium Octeon:
  - Remove usage of cvmx_wait() in favour of __delay()

  ImgTec Pistachio:
  - DT: Drop deprecated dwmmc num-slots property

  Ingenic JZ4780:
  - Add NFS root to Ci20 defconfig
  - Add watchdog to Ci20 DT & defconfig, and allow building of watchdog
    driver with this SoC

  Generic (multiplatform):
  - Migrate xilfpga (MIPSfpga) platform to the generic platform

  Lantiq xway:
  - Fix ASC0/ASC1 clocks"

* tag 'mips_4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips: (46 commits)
  MIPS: Add iomem resource for kernel bss section.
  MIPS: cmpxchg64() and HAVE_VIRT_CPU_ACCOUNTING_GEN don't work for 32-bit SMP
  MIPS: BMIPS: Enable HARDIRQS_SW_RESEND
  MIPS: pci: Make use of the BIT() macro inside the mt7620 driver
  MIPS: pci: Remove KERN_WARN instance inside the mt7620 driver
  MIPS: pci: Remove duplicate define in mt7620 driver
  MIPS: ralink: Fix typo in mt7628 pinmux function
  MIPS: ralink: Fix MT7628 pinmux
  MIPS: Fix odd fp register warnings with MIPS64r2
  watchdog: jz4780: Allow selection of jz4740-wdt driver
  MIPS/ptrace: Update syscall nr on register changes
  MIPS/ptrace: Pick up ptrace/seccomp changed syscalls
  MIPS: Fix an n32 core file generation regset support regression
  MIPS: Fix MIPS64 FP save/restore on 32-bit kernels
  MIPS: page.h: Define virt_to_pfn()
  MIPS: Xilfpga: Switch to using generic defconfigs
  MIPS: generic: Add support for MIPSfpga
  MIPS: Set defconfig target to a generic system for 32r2el
  MIPS: Kconfig: Set default MIPS system type as generic
  MIPS: DTS: Remove num-slots from Pistachio SoC
  ...
This commit is contained in:
Linus Torvalds
2017-11-15 11:36:08 -08:00
parent c9b012e5f4 e0c5f36b2a
commit 892204e06c
72 changed files with 514 additions and 436 deletions
Download Patch File Download Diff File Expand all files Collapse all files

242
arch/mips/bcm63xx/clk.c
View File

@@ -11,6 +11,7 @@
#include <linux/mutex.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/delay.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_io.h>
@@ -120,22 +121,57 @@ static struct clk clk_ephy = {
.set = ephy_set,
};
/*
* Ethernet switch SAR clock
*/
static void swpkt_sar_set(struct clk *clk, int enable)
{
if (BCMCPU_IS_6368())
bcm_hwclock_set(CKCTL_6368_SWPKT_SAR_EN, enable);
else
return;
}
static struct clk clk_swpkt_sar = {
.set = swpkt_sar_set,
};
/*
* Ethernet switch USB clock
*/
static void swpkt_usb_set(struct clk *clk, int enable)
{
if (BCMCPU_IS_6368())
bcm_hwclock_set(CKCTL_6368_SWPKT_USB_EN, enable);
else
return;
}
static struct clk clk_swpkt_usb = {
.set = swpkt_usb_set,
};
/*
* Ethernet switch clock
*/
static void enetsw_set(struct clk *clk, int enable)
{
if (BCMCPU_IS_6328())
if (BCMCPU_IS_6328()) {
bcm_hwclock_set(CKCTL_6328_ROBOSW_EN, enable);
else if (BCMCPU_IS_6362())
} else if (BCMCPU_IS_6362()) {
bcm_hwclock_set(CKCTL_6362_ROBOSW_EN, enable);
else if (BCMCPU_IS_6368())
bcm_hwclock_set(CKCTL_6368_ROBOSW_EN |
CKCTL_6368_SWPKT_USB_EN |
CKCTL_6368_SWPKT_SAR_EN,
enable);
else
} else if (BCMCPU_IS_6368()) {
if (enable) {
clk_enable_unlocked(&clk_swpkt_sar);
clk_enable_unlocked(&clk_swpkt_usb);
} else {
clk_disable_unlocked(&clk_swpkt_usb);
clk_disable_unlocked(&clk_swpkt_sar);
}
bcm_hwclock_set(CKCTL_6368_ROBOSW_EN, enable);
} else {
return;
}
if (enable) {
/* reset switch core afer clock change */
@@ -247,6 +283,10 @@ static struct clk clk_hsspi = {
.set = hsspi_set,
};
/*
* HSSPI PLL
*/
static struct clk clk_hsspi_pll;
/*
* XTM clock
@@ -256,8 +296,12 @@ static void xtm_set(struct clk *clk, int enable)
if (!BCMCPU_IS_6368())
return;
bcm_hwclock_set(CKCTL_6368_SAR_EN |
CKCTL_6368_SWPKT_SAR_EN, enable);
if (enable)
clk_enable_unlocked(&clk_swpkt_sar);
else
clk_disable_unlocked(&clk_swpkt_sar);
bcm_hwclock_set(CKCTL_6368_SAR_EN, enable);
if (enable) {
/* reset sar core afer clock change */
@@ -359,44 +403,128 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
}
EXPORT_SYMBOL_GPL(clk_round_rate);
struct clk *clk_get(struct device *dev, const char *id)
{
if (!strcmp(id, "enet0"))
return &clk_enet0;
if (!strcmp(id, "enet1"))
return &clk_enet1;
if (!strcmp(id, "enetsw"))
return &clk_enetsw;
if (!strcmp(id, "ephy"))
return &clk_ephy;
if (!strcmp(id, "usbh"))
return &clk_usbh;
if (!strcmp(id, "usbd"))
return &clk_usbd;
if (!strcmp(id, "spi"))
return &clk_spi;
if (!strcmp(id, "hsspi"))
return &clk_hsspi;
if (!strcmp(id, "xtm"))
return &clk_xtm;
if (!strcmp(id, "periph"))
return &clk_periph;
if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm"))
return &clk_pcm;
if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec"))
return &clk_ipsec;
if ((BCMCPU_IS_6328() || BCMCPU_IS_6362()) && !strcmp(id, "pcie"))
return &clk_pcie;
return ERR_PTR(-ENOENT);
}
static struct clk_lookup bcm3368_clks[] = {
/* fixed rate clocks */
CLKDEV_INIT(NULL, "periph", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
/* gated clocks */
CLKDEV_INIT(NULL, "enet0", &clk_enet0),
CLKDEV_INIT(NULL, "enet1", &clk_enet1),
CLKDEV_INIT(NULL, "ephy", &clk_ephy),
CLKDEV_INIT(NULL, "usbh", &clk_usbh),
CLKDEV_INIT(NULL, "usbd", &clk_usbd),
CLKDEV_INIT(NULL, "spi", &clk_spi),
CLKDEV_INIT(NULL, "pcm", &clk_pcm),
CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet0),
CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1),
};
EXPORT_SYMBOL(clk_get);
static struct clk_lookup bcm6328_clks[] = {
/* fixed rate clocks */
CLKDEV_INIT(NULL, "periph", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
/* gated clocks */
CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
CLKDEV_INIT(NULL, "usbh", &clk_usbh),
CLKDEV_INIT(NULL, "usbd", &clk_usbd),
CLKDEV_INIT(NULL, "hsspi", &clk_hsspi),
CLKDEV_INIT(NULL, "pcie", &clk_pcie),
};
void clk_put(struct clk *clk)
{
}
static struct clk_lookup bcm6338_clks[] = {
/* fixed rate clocks */
CLKDEV_INIT(NULL, "periph", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
/* gated clocks */
CLKDEV_INIT(NULL, "enet0", &clk_enet0),
CLKDEV_INIT(NULL, "enet1", &clk_enet1),
CLKDEV_INIT(NULL, "ephy", &clk_ephy),
CLKDEV_INIT(NULL, "usbh", &clk_usbh),
CLKDEV_INIT(NULL, "usbd", &clk_usbd),
CLKDEV_INIT(NULL, "spi", &clk_spi),
CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
};
EXPORT_SYMBOL(clk_put);
static struct clk_lookup bcm6345_clks[] = {
/* fixed rate clocks */
CLKDEV_INIT(NULL, "periph", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
/* gated clocks */
CLKDEV_INIT(NULL, "enet0", &clk_enet0),
CLKDEV_INIT(NULL, "enet1", &clk_enet1),
CLKDEV_INIT(NULL, "ephy", &clk_ephy),
CLKDEV_INIT(NULL, "usbh", &clk_usbh),
CLKDEV_INIT(NULL, "usbd", &clk_usbd),
CLKDEV_INIT(NULL, "spi", &clk_spi),
CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
};
static struct clk_lookup bcm6348_clks[] = {
/* fixed rate clocks */
CLKDEV_INIT(NULL, "periph", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
/* gated clocks */
CLKDEV_INIT(NULL, "enet0", &clk_enet0),
CLKDEV_INIT(NULL, "enet1", &clk_enet1),
CLKDEV_INIT(NULL, "ephy", &clk_ephy),
CLKDEV_INIT(NULL, "usbh", &clk_usbh),
CLKDEV_INIT(NULL, "usbd", &clk_usbd),
CLKDEV_INIT(NULL, "spi", &clk_spi),
CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet_misc),
};
static struct clk_lookup bcm6358_clks[] = {
/* fixed rate clocks */
CLKDEV_INIT(NULL, "periph", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
/* gated clocks */
CLKDEV_INIT(NULL, "enet0", &clk_enet0),
CLKDEV_INIT(NULL, "enet1", &clk_enet1),
CLKDEV_INIT(NULL, "ephy", &clk_ephy),
CLKDEV_INIT(NULL, "usbh", &clk_usbh),
CLKDEV_INIT(NULL, "usbd", &clk_usbd),
CLKDEV_INIT(NULL, "spi", &clk_spi),
CLKDEV_INIT(NULL, "pcm", &clk_pcm),
CLKDEV_INIT(NULL, "swpkt_sar", &clk_swpkt_sar),
CLKDEV_INIT(NULL, "swpkt_usb", &clk_swpkt_usb),
CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet0),
CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1),
};
static struct clk_lookup bcm6362_clks[] = {
/* fixed rate clocks */
CLKDEV_INIT(NULL, "periph", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
/* gated clocks */
CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
CLKDEV_INIT(NULL, "usbh", &clk_usbh),
CLKDEV_INIT(NULL, "usbd", &clk_usbd),
CLKDEV_INIT(NULL, "spi", &clk_spi),
CLKDEV_INIT(NULL, "hsspi", &clk_hsspi),
CLKDEV_INIT(NULL, "pcie", &clk_pcie),
CLKDEV_INIT(NULL, "ipsec", &clk_ipsec),
};
static struct clk_lookup bcm6368_clks[] = {
/* fixed rate clocks */
CLKDEV_INIT(NULL, "periph", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
/* gated clocks */
CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
CLKDEV_INIT(NULL, "usbh", &clk_usbh),
CLKDEV_INIT(NULL, "usbd", &clk_usbd),
CLKDEV_INIT(NULL, "spi", &clk_spi),
CLKDEV_INIT(NULL, "xtm", &clk_xtm),
CLKDEV_INIT(NULL, "ipsec", &clk_ipsec),
};
#define HSSPI_PLL_HZ_6328 133333333
#define HSSPI_PLL_HZ_6362 400000000
@@ -404,11 +532,31 @@ EXPORT_SYMBOL(clk_put);
static int __init bcm63xx_clk_init(void)
{
switch (bcm63xx_get_cpu_id()) {
case BCM3368_CPU_ID:
clkdev_add_table(bcm3368_clks, ARRAY_SIZE(bcm3368_clks));
break;
case BCM6328_CPU_ID:
clk_hsspi.rate = HSSPI_PLL_HZ_6328;
clk_hsspi_pll.rate = HSSPI_PLL_HZ_6328;
clkdev_add_table(bcm6328_clks, ARRAY_SIZE(bcm6328_clks));
break;
case BCM6338_CPU_ID:
clkdev_add_table(bcm6338_clks, ARRAY_SIZE(bcm6338_clks));
break;
case BCM6345_CPU_ID:
clkdev_add_table(bcm6345_clks, ARRAY_SIZE(bcm6345_clks));
break;
case BCM6348_CPU_ID:
clkdev_add_table(bcm6348_clks, ARRAY_SIZE(bcm6348_clks));
break;
case BCM6358_CPU_ID:
clkdev_add_table(bcm6358_clks, ARRAY_SIZE(bcm6358_clks));
break;
case BCM6362_CPU_ID:
clk_hsspi.rate = HSSPI_PLL_HZ_6362;
clk_hsspi_pll.rate = HSSPI_PLL_HZ_6362;
clkdev_add_table(bcm6362_clks, ARRAY_SIZE(bcm6362_clks));
break;
case BCM6368_CPU_ID:
clkdev_add_table(bcm6368_clks, ARRAY_SIZE(bcm6368_clks));
break;
}