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MIPS: OCTEON: Add support for cn68XX interrupt controller.

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The cn68XX has a new interrupt controller named CIU2, add support for
this, and use it if cn68XX detected at runtime.

Signed-off-by: David Daney <david.daney@cavium.com>
This commit is contained in:
David Daney
2012-04-04 15:34:41 -07:00
parent 9787c56ee3
commit 88fd85892a
2 changed files with 547 additions and 24 deletions
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arch/mips/include/asm/octeon/octeon.h
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@@ -254,4 +254,7 @@ extern uint64_t octeon_bootloader_entry_addr;
extern void (*octeon_irq_setup_secondary)(void);
typedef void (*octeon_irq_ip4_handler_t)(void);
void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t);
#endif /* __ASM_OCTEON_OCTEON_H */