Merge tag 'drm-intel-next-2014-04-16' of git://anongit.freedesktop.org/drm-intel into drm-next
drm-intel-next-2014-04-16: - vlv infoframe fixes from Jesse - dsi/mipi fixes from Shobhit - gen8 pageflip fixes for LRI/SRM from Damien - cmd parser fixes from Brad Volkin - some prep patches for CHV, DRRS, ... - and tons of little things all over drm-intel-next-2014-04-04: - cmd parser for gen7 but only in enforcing and not yet granting mode - the batch copying stuff is still missing. Also performance is a bit ... rough (Brad Volkin + OACONTROL fix from Ken). - deprecate UMS harder (i.e. CONFIG_BROKEN) - interrupt rework from Paulo Zanoni - runtime PM support for bdw and snb, again from Paulo - a pile of refactorings from various people all over the place to prep for new stuff (irq reworks, power domain polish, ...) drm-intel-next-2014-04-04: - cmd parser for gen7 but only in enforcing and not yet granting mode - the batch copying stuff is still missing. Also performance is a bit ... rough (Brad Volkin + OACONTROL fix from Ken). - deprecate UMS harder (i.e. CONFIG_BROKEN) - interrupt rework from Paulo Zanoni - runtime PM support for bdw and snb, again from Paulo - a pile of refactorings from various people all over the place to prep for new stuff (irq reworks, power domain polish, ...) Conflicts: drivers/gpu/drm/i915/i915_gem_context.c
This commit is contained in:
Dave Airlie
@@ -738,6 +738,20 @@ intel_dp_set_clock(struct intel_encoder *encoder,
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}
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}
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static void
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intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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enum transcoder transcoder = crtc->config.cpu_transcoder;
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I915_WRITE(PIPE_DATA_M2(transcoder),
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TU_SIZE(m_n->tu) | m_n->gmch_m);
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I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
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I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
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I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
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}
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bool
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intel_dp_compute_config(struct intel_encoder *encoder,
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struct intel_crtc_config *pipe_config)
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@@ -842,6 +856,14 @@ found:
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pipe_config->port_clock,
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&pipe_config->dp_m_n);
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if (intel_connector->panel.downclock_mode != NULL &&
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intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
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intel_link_compute_m_n(bpp, lane_count,
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intel_connector->panel.downclock_mode->clock,
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pipe_config->port_clock,
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&pipe_config->dp_m2_n2);
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}
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intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
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return true;
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@@ -1044,7 +1066,10 @@ static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
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static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
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{
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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struct intel_encoder *intel_encoder = &intel_dig_port->base;
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struct drm_i915_private *dev_priv = dev->dev_private;
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enum intel_display_power_domain power_domain;
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u32 pp;
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u32 pp_stat_reg, pp_ctrl_reg;
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bool need_to_disable = !intel_dp->want_panel_vdd;
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@@ -1057,7 +1082,8 @@ static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
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if (edp_have_panel_vdd(intel_dp))
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return need_to_disable;
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intel_runtime_pm_get(dev_priv);
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power_domain = intel_display_port_power_domain(intel_encoder);
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intel_display_power_get(dev_priv, power_domain);
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DRM_DEBUG_KMS("Turning eDP VDD on\n");
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@@ -1104,6 +1130,11 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
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WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
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if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
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struct intel_digital_port *intel_dig_port =
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dp_to_dig_port(intel_dp);
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struct intel_encoder *intel_encoder = &intel_dig_port->base;
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enum intel_display_power_domain power_domain;
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DRM_DEBUG_KMS("Turning eDP VDD off\n");
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pp = ironlake_get_pp_control(intel_dp);
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@@ -1122,7 +1153,8 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
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if ((pp & POWER_TARGET_ON) == 0)
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intel_dp->last_power_cycle = jiffies;
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intel_runtime_pm_put(dev_priv);
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power_domain = intel_display_port_power_domain(intel_encoder);
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intel_display_power_put(dev_priv, power_domain);
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}
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}
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@@ -1206,8 +1238,11 @@ void intel_edp_panel_on(struct intel_dp *intel_dp)
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void intel_edp_panel_off(struct intel_dp *intel_dp)
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{
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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struct intel_encoder *intel_encoder = &intel_dig_port->base;
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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struct drm_i915_private *dev_priv = dev->dev_private;
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enum intel_display_power_domain power_domain;
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u32 pp;
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u32 pp_ctrl_reg;
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@@ -1237,7 +1272,8 @@ void intel_edp_panel_off(struct intel_dp *intel_dp)
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wait_panel_off(intel_dp);
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/* We got a reference when we enabled the VDD. */
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intel_runtime_pm_put(dev_priv);
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power_domain = intel_display_port_power_domain(intel_encoder);
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intel_display_power_put(dev_priv, power_domain);
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}
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void intel_edp_backlight_on(struct intel_dp *intel_dp)
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@@ -1778,17 +1814,23 @@ static void intel_disable_dp(struct intel_encoder *encoder)
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intel_dp_link_down(intel_dp);
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}
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static void intel_post_disable_dp(struct intel_encoder *encoder)
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static void g4x_post_disable_dp(struct intel_encoder *encoder)
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{
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struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
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enum port port = dp_to_dig_port(intel_dp)->port;
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struct drm_device *dev = encoder->base.dev;
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if (port == PORT_A || IS_VALLEYVIEW(dev)) {
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intel_dp_link_down(intel_dp);
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if (!IS_VALLEYVIEW(dev))
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ironlake_edp_pll_off(intel_dp);
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}
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if (port != PORT_A)
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return;
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intel_dp_link_down(intel_dp);
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ironlake_edp_pll_off(intel_dp);
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}
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static void vlv_post_disable_dp(struct intel_encoder *encoder)
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{
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struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
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intel_dp_link_down(intel_dp);
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}
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static void intel_enable_dp(struct intel_encoder *encoder)
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@@ -3613,6 +3655,130 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
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I915_READ(pp_div_reg));
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}
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void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_encoder *encoder;
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struct intel_dp *intel_dp = NULL;
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struct intel_crtc_config *config = NULL;
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struct intel_crtc *intel_crtc = NULL;
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struct intel_connector *intel_connector = dev_priv->drrs.connector;
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u32 reg, val;
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enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
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if (refresh_rate <= 0) {
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DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
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return;
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}
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if (intel_connector == NULL) {
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DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
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return;
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}
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if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
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DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
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return;
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}
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encoder = intel_attached_encoder(&intel_connector->base);
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intel_dp = enc_to_intel_dp(&encoder->base);
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intel_crtc = encoder->new_crtc;
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if (!intel_crtc) {
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DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
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return;
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}
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config = &intel_crtc->config;
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if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
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DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
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return;
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}
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if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
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index = DRRS_LOW_RR;
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if (index == intel_dp->drrs_state.refresh_rate_type) {
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DRM_DEBUG_KMS(
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"DRRS requested for previously set RR...ignoring\n");
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return;
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}
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if (!intel_crtc->active) {
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DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
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return;
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}
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if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
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reg = PIPECONF(intel_crtc->config.cpu_transcoder);
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val = I915_READ(reg);
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if (index > DRRS_HIGH_RR) {
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val |= PIPECONF_EDP_RR_MODE_SWITCH;
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intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
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} else {
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val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
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}
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I915_WRITE(reg, val);
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}
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/*
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* mutex taken to ensure that there is no race between differnt
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* drrs calls trying to update refresh rate. This scenario may occur
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* in future when idleness detection based DRRS in kernel and
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* possible calls from user space to set differnt RR are made.
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*/
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mutex_lock(&intel_dp->drrs_state.mutex);
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intel_dp->drrs_state.refresh_rate_type = index;
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mutex_unlock(&intel_dp->drrs_state.mutex);
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DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
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}
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static struct drm_display_mode *
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intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
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struct intel_connector *intel_connector,
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struct drm_display_mode *fixed_mode)
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{
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struct drm_connector *connector = &intel_connector->base;
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struct intel_dp *intel_dp = &intel_dig_port->dp;
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struct drm_device *dev = intel_dig_port->base.base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_display_mode *downclock_mode = NULL;
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if (INTEL_INFO(dev)->gen <= 6) {
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DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
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return NULL;
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}
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if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
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DRM_INFO("VBT doesn't support DRRS\n");
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return NULL;
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}
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downclock_mode = intel_find_panel_downclock
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(dev, fixed_mode, connector);
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if (!downclock_mode) {
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DRM_INFO("DRRS not supported\n");
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return NULL;
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}
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dev_priv->drrs.connector = intel_connector;
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mutex_init(&intel_dp->drrs_state.mutex);
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intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
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intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
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DRM_INFO("seamless DRRS supported for eDP panel.\n");
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return downclock_mode;
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}
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static bool intel_edp_init_connector(struct intel_dp *intel_dp,
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struct intel_connector *intel_connector,
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struct edp_power_seq *power_seq)
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@@ -3623,10 +3789,13 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
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struct drm_device *dev = intel_encoder->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_display_mode *fixed_mode = NULL;
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struct drm_display_mode *downclock_mode = NULL;
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bool has_dpcd;
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struct drm_display_mode *scan;
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struct edid *edid;
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intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
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if (!is_edp(intel_dp))
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return true;
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@@ -3677,6 +3846,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
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list_for_each_entry(scan, &connector->probed_modes, head) {
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if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
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fixed_mode = drm_mode_duplicate(dev, scan);
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downclock_mode = intel_dp_drrs_init(
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intel_dig_port,
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intel_connector, fixed_mode);
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break;
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}
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}
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@@ -3690,7 +3862,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
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}
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mutex_unlock(&dev->mode_config.mutex);
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intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
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intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
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intel_panel_setup_backlight(connector);
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return true;
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@@ -3841,16 +4013,17 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
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intel_encoder->compute_config = intel_dp_compute_config;
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intel_encoder->mode_set = intel_dp_mode_set;
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intel_encoder->disable = intel_disable_dp;
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intel_encoder->post_disable = intel_post_disable_dp;
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intel_encoder->get_hw_state = intel_dp_get_hw_state;
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intel_encoder->get_config = intel_dp_get_config;
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if (IS_VALLEYVIEW(dev)) {
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intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
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intel_encoder->pre_enable = vlv_pre_enable_dp;
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intel_encoder->enable = vlv_enable_dp;
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intel_encoder->post_disable = vlv_post_disable_dp;
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} else {
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intel_encoder->pre_enable = g4x_pre_enable_dp;
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intel_encoder->enable = g4x_enable_dp;
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intel_encoder->post_disable = g4x_post_disable_dp;
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}
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intel_dig_port->port = port;
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