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clk: exynos5420: Add IDs for clocks used in DISP1 power domain

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When a power domain is powered off on Exynos5420 SoC, the input clocks of
the devices attached to this power domain are re-parented to oscclk and
restored to the original parent after powering on the power domain.

So a reference to the input and parent clocks for the devices attached to
a power domain are needed to be able to do the re-parenting. The DISP1 pd
includes modules which uses the following clocks:

ACLK_200_DISP1 (MIXER and HDMILINK)
ACLK_300_DISP1 (FIMD1)
ACLK_400_DISP1 (Internal Buses)

Each of these clocks are generated as the output of a clock mux so add an
ID for all of these clock muxes and their parents to be referenced in the
DISP1 power domain device node.

Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
This commit is contained in:
Javier Martinez Canillas
2015-01-24 13:25:01 +09:00
committed by Kukjin Kim
parent 6591a02e17
commit 8856010029
2 changed files with 18 additions and 11 deletions
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6
include/dt-bindings/clock/exynos5420.h
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@@ -204,6 +204,12 @@
#define CLK_MOUT_MAUDIO0 643
#define CLK_MOUT_USER_ACLK333 644
#define CLK_MOUT_SW_ACLK333 645
#define CLK_MOUT_USER_ACLK200_DISP1 646
#define CLK_MOUT_SW_ACLK200 647
#define CLK_MOUT_USER_ACLK300_DISP1 648
#define CLK_MOUT_SW_ACLK300 649
#define CLK_MOUT_USER_ACLK400_DISP1 650
#define CLK_MOUT_SW_ACLK400 651
/* divider clocks */
#define CLK_DOUT_PIXEL 768