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drivers: clk: st: Simplify clock binding of STiH4xx platforms

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This patch reworks the clock binding to avoid too much detail in DT.
Now we have only compatible string per type of clock
(remark from Rob https://lkml.org/lkml/2016/5/25/492)

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Gabriel Fernandez
2016-08-29 14:26:54 +02:00
committed by Stephen Boyd
parent 7df404c985
commit 880d54ff56
7 changed files with 65 additions and 88 deletions
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2
Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
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@@ -10,7 +10,7 @@ This binding uses the common clock binding[1].
Required properties:
- compatible : shall be:
"st,stih407-clkgen-a9-mux", "st,clkgen-mux"
"st,stih407-clkgen-a9-mux"
- #clock-cells : from common clock binding; shall be set to 0.

11
Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
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@@ -9,11 +9,10 @@ Base address is located to the parent node. See clock binding[2]
Required properties:
- compatible : shall be:
"st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
"sst,plls-c32-cx_0", "st,clkgen-plls-c32"
"sst,plls-c32-cx_1", "st,clkgen-plls-c32"
"st,stih418-plls-c28-a9", "st,clkgen-plls-c32"
"st,clkgen-pll0"
"st,clkgen-pll1"
"st,stih407-clkgen-plla9"
"st,stih418-clkgen-plla9"
- #clock-cells : From common clock binding; shall be set to 1.
@@ -29,7 +28,7 @@ Example:
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
compatible = "st,stih407-clkgen-plla9";
clocks = <&clk_sysin>;

2
Documentation/devicetree/bindings/clock/st/st,clkgen.txt
View File

@@ -48,7 +48,7 @@ Example:
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
compatible = "st,clkgen-pll0";
clocks = <&clk_sysin>;

6
Documentation/devicetree/bindings/clock/st/st,quadfs.txt
View File

@@ -11,8 +11,8 @@ This binding uses the common clock binding[1].
Required properties:
- compatible : shall be:
"st,stih407-quadfs660-C", "st,quadfs"
"st,stih407-quadfs660-D", "st,quadfs"
"st,quadfs"
"st,quadfs-pll"
- #clock-cells : from common clock binding; shall be set to 1.
@@ -33,7 +33,7 @@ Example:
clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
#clock-cells = <1>;
compatible = "st,stih407-quadfs660-C", "st,quadfs";
compatible = "st,quadfs-pll";
reg = <0x9103000 0x1000>;
clocks = <&clk_sysin>;