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drm/i915/cml: Separate U series pci id from origianl list.

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U series device need different DDI buffer setup for eDP
and DP. If driver did not recognize ULT id proerply.
The setting for H and S series would be used.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191210150415.10705-2-shawn.c.lee@intel.com
This commit is contained in:
Lee Shawn C
2019-12-10 23:04:15 +08:00
committed by Ville Syrjälä
parent b6a8781a44
commit 8717c6b741
3 changed files with 17 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
include/drm/i915_pciids.h
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@@ -446,19 +446,18 @@
/* CML GT1 */
#define INTEL_CML_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x9B21, info), \
INTEL_VGA_DEVICE(0x9BAA, info), \
INTEL_VGA_DEVICE(0x9BAC, info), \
INTEL_VGA_DEVICE(0x9BA5, info), \
INTEL_VGA_DEVICE(0x9BA8, info), \
INTEL_VGA_DEVICE(0x9BA4, info), \
INTEL_VGA_DEVICE(0x9BA2, info)
#define INTEL_CML_U_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x9B21, info), \
INTEL_VGA_DEVICE(0x9BAA, info), \
INTEL_VGA_DEVICE(0x9BAC, info)
/* CML GT2 */
#define INTEL_CML_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x9B41, info), \
INTEL_VGA_DEVICE(0x9BCA, info), \
INTEL_VGA_DEVICE(0x9BCC, info), \
INTEL_VGA_DEVICE(0x9BC5, info), \
INTEL_VGA_DEVICE(0x9BC8, info), \
INTEL_VGA_DEVICE(0x9BC4, info), \
@@ -467,6 +466,11 @@
INTEL_VGA_DEVICE(0x9BE6, info), \
INTEL_VGA_DEVICE(0x9BF6, info)
#define INTEL_CML_U_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x9B41, info), \
INTEL_VGA_DEVICE(0x9BCA, info), \
INTEL_VGA_DEVICE(0x9BCC, info)
#define INTEL_KBL_IDS(info) \
INTEL_KBL_GT1_IDS(info), \
INTEL_KBL_GT2_IDS(info), \
@@ -532,7 +536,9 @@
INTEL_WHL_U_GT3_IDS(info), \
INTEL_AML_CFL_GT2_IDS(info), \
INTEL_CML_GT1_IDS(info), \
INTEL_CML_GT2_IDS(info)
INTEL_CML_GT2_IDS(info), \
INTEL_CML_U_GT1_IDS(info), \
INTEL_CML_U_GT2_IDS(info)
/* CNL */
#define INTEL_CNL_PORT_F_IDS(info) \