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Merge tag 'renesas-drivers-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers

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Renesas ARM Based SoC Drivers Updates for v4.20

* Convert to SPDX identifiers
* R-Car V3M (r8a77970) and V3H (r8a77980): Document Timer Unit (TMU) bindings
* RZ/G1N (r8a7744) and RZ/G1C (r8a77470) SoCs:
  - Document APMU and SMP enable method
* RZ/G2M (r8a74a1), RZ/G1N (r8a7744) and RZ/G2E (r8a774c0) SoCs:
  - Add reset support
  - Add sysc support
* RZ/G2M (r8a774a1), RZ/G2E (r8a774c0) and RZ/A2M (r7s9210) SoCs:
  - Add support for identifying SoC
* RZ/A2M (r7s9210) SoC:
  - Add basic SoC setup support

* tag 'renesas-drivers-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (21 commits)
  dt-bindings: apmu: Document r8a7744 support
  dt-bindings: timer: renesas: tmu: document R8A779{7|8}0 bindings
  dt-bindings: apmu: Document r8a77470 support
  soc: renesas: rcar-rst: Add support for RZ/G1N
  dt-bindings: reset: rcar-rst: Document r8a7744 reset module
  soc: renesas: rcar-sysc: Add r8a7744 support
  dt-bindings: power: rcar-sysc: Add r8a7744 power domain index macros
  dt-bindings: power: rcar-sysc: Document r8a7744 SYSC binding
  soc: renesas: rcar-rst: Add support for RZ/G2E
  dt-bindings: reset: rcar-rst: Document r8a774c0 rst
  soc: renesas: rcar-sysc: Add r8a774c0 support
  dt-bindings: power: rcar-sysc: Document r8a774c0 sysc
  dt-bindings: power: Add r8a774c0 SYSC power domain definitions
  soc: renesas: Identify RZ/G2E
  soc: renesas: convert to SPDX identifiers
  soc: renesas: rcar-rst: Add support for RZ/G2M
  soc: renesas: rcar-sysc: Add r8a774a1 support
  dt-bindings: power: Add r8a774a1 SYSC power domain definitions
  soc: renesas: identify RZ/A2
  ARM: shmobile: Add basic RZ/A2 SoC support
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2018-09-28 22:16:47 +02:00
parent ab2dc8446a fae210bb5b
commit 86e762d967
29 changed files with 360 additions and 86 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
include/dt-bindings/power/r8a7744-sysc.h Normal file
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/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A7744_SYSC_H__
#define __DT_BINDINGS_POWER_R8A7744_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*
* Note that RZ/G1N is identical to RZ/G2M w.r.t. power domains.
*/
#define R8A7744_PD_CA15_CPU0 0
#define R8A7744_PD_CA15_CPU1 1
#define R8A7744_PD_CA15_SCU 12
#define R8A7744_PD_SGX 20
/* Always-on power area */
#define R8A7744_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A7744_SYSC_H__ */

31
include/dt-bindings/power/r8a774a1-sysc.h Normal file
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/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A774A1_SYSC_H__
#define __DT_BINDINGS_POWER_R8A774A1_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A774A1_PD_CA57_CPU0 0
#define R8A774A1_PD_CA57_CPU1 1
#define R8A774A1_PD_CA53_CPU0 5
#define R8A774A1_PD_CA53_CPU1 6
#define R8A774A1_PD_CA53_CPU2 7
#define R8A774A1_PD_CA53_CPU3 8
#define R8A774A1_PD_CA57_SCU 12
#define R8A774A1_PD_A3VC 14
#define R8A774A1_PD_3DG_A 17
#define R8A774A1_PD_3DG_B 18
#define R8A774A1_PD_CA53_SCU 21
#define R8A774A1_PD_A2VC0 25
#define R8A774A1_PD_A2VC1 26
/* Always-on power area */
#define R8A774A1_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ */

25
include/dt-bindings/power/r8a774c0-sysc.h Normal file
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/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A774C0_SYSC_H__
#define __DT_BINDINGS_POWER_R8A774C0_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A774C0_PD_CA53_CPU0 5
#define R8A774C0_PD_CA53_CPU1 6
#define R8A774C0_PD_A3VC 14
#define R8A774C0_PD_3DG_A 17
#define R8A774C0_PD_3DG_B 18
#define R8A774C0_PD_CA53_SCU 21
#define R8A774C0_PD_A2VC1 26
/* Always-on power area */
#define R8A774C0_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A774C0_SYSC_H__ */