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clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate

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This removes the conversion from pdiv to hw, which is already taken
care of by _get_table_rate before this code is run. This avoids
incorrectly converting pdiv to hw twice and getting the wrong hw value.

Also set the input_rate in the freq cfg in _calc_dynamic_ramp_rate while
setting all the other fields.

In order to prevent regressions on earlier SoC generations, all of the
frequency tables need to be updated so that they contain the actual
divider values. If they contain hardware values these would be converted
to hardware values again, yielding the wrong value.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
[treding@nvidia.com: fix regressions on earlier SoC generations]
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Rhyland Klein
2015-06-18 17:28:34 -04:00
committed by Thierry Reding
父節點 fde207eb15
當前提交 86c679a522
共有 5 個文件被更改，包括 379 次插入 和 304 次删除
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227
drivers/clk/tegra/clk-tegra30.c
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@@ -248,87 +248,87 @@ static const struct utmi_clk_param utmi_parameters[] = {
};
static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
{ 12000000, 1040000000, 520, 6, 0, 8 },
{ 13000000, 1040000000, 480, 6, 0, 8 },
{ 16800000, 1040000000, 495, 8, 0, 8 }, /* actual: 1039.5 MHz */
{ 19200000, 1040000000, 325, 6, 0, 6 },
{ 26000000, 1040000000, 520, 13, 0, 8 },
{ 12000000, 832000000, 416, 6, 0, 8 },
{ 13000000, 832000000, 832, 13, 0, 8 },
{ 16800000, 832000000, 396, 8, 0, 8 }, /* actual: 831.6 MHz */
{ 19200000, 832000000, 260, 6, 0, 8 },
{ 26000000, 832000000, 416, 13, 0, 8 },
{ 12000000, 624000000, 624, 12, 0, 8 },
{ 13000000, 624000000, 624, 13, 0, 8 },
{ 16800000, 600000000, 520, 14, 0, 8 },
{ 19200000, 624000000, 520, 16, 0, 8 },
{ 26000000, 624000000, 624, 26, 0, 8 },
{ 12000000, 600000000, 600, 12, 0, 8 },
{ 13000000, 600000000, 600, 13, 0, 8 },
{ 16800000, 600000000, 500, 14, 0, 8 },
{ 19200000, 600000000, 375, 12, 0, 6 },
{ 26000000, 600000000, 600, 26, 0, 8 },
{ 12000000, 520000000, 520, 12, 0, 8 },
{ 13000000, 520000000, 520, 13, 0, 8 },
{ 16800000, 520000000, 495, 16, 0, 8 }, /* actual: 519.75 MHz */
{ 19200000, 520000000, 325, 12, 0, 6 },
{ 26000000, 520000000, 520, 26, 0, 8 },
{ 12000000, 416000000, 416, 12, 0, 8 },
{ 13000000, 416000000, 416, 13, 0, 8 },
{ 16800000, 416000000, 396, 16, 0, 8 }, /* actual: 415.8 MHz */
{ 19200000, 416000000, 260, 12, 0, 6 },
{ 26000000, 416000000, 416, 26, 0, 8 },
{ 12000000, 1040000000, 520, 6, 1, 8 },
{ 13000000, 1040000000, 480, 6, 1, 8 },
{ 16800000, 1040000000, 495, 8, 1, 8 }, /* actual: 1039.5 MHz */
{ 19200000, 1040000000, 325, 6, 1, 6 },
{ 26000000, 1040000000, 520, 13, 1, 8 },
{ 12000000, 832000000, 416, 6, 1, 8 },
{ 13000000, 832000000, 832, 13, 1, 8 },
{ 16800000, 832000000, 396, 8, 1, 8 }, /* actual: 831.6 MHz */
{ 19200000, 832000000, 260, 6, 1, 8 },
{ 26000000, 832000000, 416, 13, 1, 8 },
{ 12000000, 624000000, 624, 12, 1, 8 },
{ 13000000, 624000000, 624, 13, 1, 8 },
{ 16800000, 600000000, 520, 14, 1, 8 },
{ 19200000, 624000000, 520, 16, 1, 8 },
{ 26000000, 624000000, 624, 26, 1, 8 },
{ 12000000, 600000000, 600, 12, 1, 8 },
{ 13000000, 600000000, 600, 13, 1, 8 },
{ 16800000, 600000000, 500, 14, 1, 8 },
{ 19200000, 600000000, 375, 12, 1, 6 },
{ 26000000, 600000000, 600, 26, 1, 8 },
{ 12000000, 520000000, 520, 12, 1, 8 },
{ 13000000, 520000000, 520, 13, 1, 8 },
{ 16800000, 520000000, 495, 16, 1, 8 }, /* actual: 519.75 MHz */
{ 19200000, 520000000, 325, 12, 1, 6 },
{ 26000000, 520000000, 520, 26, 1, 8 },
{ 12000000, 416000000, 416, 12, 1, 8 },
{ 13000000, 416000000, 416, 13, 1, 8 },
{ 16800000, 416000000, 396, 16, 1, 8 }, /* actual: 415.8 MHz */
{ 19200000, 416000000, 260, 12, 1, 6 },
{ 26000000, 416000000, 416, 26, 1, 8 },
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
{ 12000000, 666000000, 666, 12, 0, 8 },
{ 13000000, 666000000, 666, 13, 0, 8 },
{ 16800000, 666000000, 555, 14, 0, 8 },
{ 19200000, 666000000, 555, 16, 0, 8 },
{ 26000000, 666000000, 666, 26, 0, 8 },
{ 12000000, 600000000, 600, 12, 0, 8 },
{ 13000000, 600000000, 600, 13, 0, 8 },
{ 16800000, 600000000, 500, 14, 0, 8 },
{ 19200000, 600000000, 375, 12, 0, 6 },
{ 26000000, 600000000, 600, 26, 0, 8 },
{ 12000000, 666000000, 666, 12, 1, 8 },
{ 13000000, 666000000, 666, 13, 1, 8 },
{ 16800000, 666000000, 555, 14, 1, 8 },
{ 19200000, 666000000, 555, 16, 1, 8 },
{ 26000000, 666000000, 666, 26, 1, 8 },
{ 12000000, 600000000, 600, 12, 1, 8 },
{ 13000000, 600000000, 600, 13, 1, 8 },
{ 16800000, 600000000, 500, 14, 1, 8 },
{ 19200000, 600000000, 375, 12, 1, 6 },
{ 26000000, 600000000, 600, 26, 1, 8 },
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
{ 12000000, 216000000, 432, 12, 1, 8 },
{ 13000000, 216000000, 432, 13, 1, 8 },
{ 16800000, 216000000, 360, 14, 1, 8 },
{ 19200000, 216000000, 360, 16, 1, 8 },
{ 26000000, 216000000, 432, 26, 1, 8 },
{ 12000000, 216000000, 432, 12, 2, 8 },
{ 13000000, 216000000, 432, 13, 2, 8 },
{ 16800000, 216000000, 360, 14, 2, 8 },
{ 19200000, 216000000, 360, 16, 2, 8 },
{ 26000000, 216000000, 432, 26, 2, 8 },
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
{ 9600000, 564480000, 294, 5, 0, 4 },
{ 9600000, 552960000, 288, 5, 0, 4 },
{ 9600000, 24000000, 5, 2, 0, 1 },
{ 28800000, 56448000, 49, 25, 0, 1 },
{ 28800000, 73728000, 64, 25, 0, 1 },
{ 28800000, 24000000, 5, 6, 0, 1 },
{ 9600000, 564480000, 294, 5, 1, 4 },
{ 9600000, 552960000, 288, 5, 1, 4 },
{ 9600000, 24000000, 5, 2, 1, 1 },
{ 28800000, 56448000, 49, 25, 1, 1 },
{ 28800000, 73728000, 64, 25, 1, 1 },
{ 28800000, 24000000, 5, 6, 1, 1 },
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
{ 12000000, 216000000, 216, 12, 0, 4 },
{ 13000000, 216000000, 216, 13, 0, 4 },
{ 16800000, 216000000, 180, 14, 0, 4 },
{ 19200000, 216000000, 180, 16, 0, 4 },
{ 26000000, 216000000, 216, 26, 0, 4 },
{ 12000000, 594000000, 594, 12, 0, 8 },
{ 13000000, 594000000, 594, 13, 0, 8 },
{ 16800000, 594000000, 495, 14, 0, 8 },
{ 19200000, 594000000, 495, 16, 0, 8 },
{ 26000000, 594000000, 594, 26, 0, 8 },
{ 12000000, 1000000000, 1000, 12, 0, 12 },
{ 13000000, 1000000000, 1000, 13, 0, 12 },
{ 19200000, 1000000000, 625, 12, 0, 8 },
{ 26000000, 1000000000, 1000, 26, 0, 12 },
{ 12000000, 216000000, 216, 12, 1, 4 },
{ 13000000, 216000000, 216, 13, 1, 4 },
{ 16800000, 216000000, 180, 14, 1, 4 },
{ 19200000, 216000000, 180, 16, 1, 4 },
{ 26000000, 216000000, 216, 26, 1, 4 },
{ 12000000, 594000000, 594, 12, 1, 8 },
{ 13000000, 594000000, 594, 13, 1, 8 },
{ 16800000, 594000000, 495, 14, 1, 8 },
{ 19200000, 594000000, 495, 16, 1, 8 },
{ 26000000, 594000000, 594, 26, 1, 8 },
{ 12000000, 1000000000, 1000, 12, 1, 12 },
{ 13000000, 1000000000, 1000, 13, 1, 12 },
{ 19200000, 1000000000, 625, 12, 1, 8 },
{ 26000000, 1000000000, 1000, 26, 1, 12 },
{ 0, 0, 0, 0, 0, 0 },
};
@@ -339,66 +339,72 @@ static const struct pdiv_map pllu_p[] = {
};
static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
{ 12000000, 480000000, 960, 12, 0, 12 },
{ 13000000, 480000000, 960, 13, 0, 12 },
{ 16800000, 480000000, 400, 7, 0, 5 },
{ 19200000, 480000000, 200, 4, 0, 3 },
{ 26000000, 480000000, 960, 26, 0, 12 },
{ 12000000, 480000000, 960, 12, 1, 12 },
{ 13000000, 480000000, 960, 13, 1, 12 },
{ 16800000, 480000000, 400, 7, 1, 5 },
{ 19200000, 480000000, 200, 4, 1, 3 },
{ 26000000, 480000000, 960, 26, 1, 12 },
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
/* 1.7 GHz */
{ 12000000, 1700000000, 850, 6, 0, 8 },
{ 13000000, 1700000000, 915, 7, 0, 8 }, /* actual: 1699.2 MHz */
{ 16800000, 1700000000, 708, 7, 0, 8 }, /* actual: 1699.2 MHz */
{ 19200000, 1700000000, 885, 10, 0, 8 }, /* actual: 1699.2 MHz */
{ 26000000, 1700000000, 850, 13, 0, 8 },
{ 12000000, 1700000000, 850, 6, 1, 8 },
{ 13000000, 1700000000, 915, 7, 1, 8 }, /* actual: 1699.2 MHz */
{ 16800000, 1700000000, 708, 7, 1, 8 }, /* actual: 1699.2 MHz */
{ 19200000, 1700000000, 885, 10, 1, 8 }, /* actual: 1699.2 MHz */
{ 26000000, 1700000000, 850, 13, 1, 8 },
/* 1.6 GHz */
{ 12000000, 1600000000, 800, 6, 0, 8 },
{ 13000000, 1600000000, 738, 6, 0, 8 }, /* actual: 1599.0 MHz */
{ 16800000, 1600000000, 857, 9, 0, 8 }, /* actual: 1599.7 MHz */
{ 19200000, 1600000000, 500, 6, 0, 8 },
{ 26000000, 1600000000, 800, 13, 0, 8 },
{ 12000000, 1600000000, 800, 6, 1, 8 },
{ 13000000, 1600000000, 738, 6, 1, 8 }, /* actual: 1599.0 MHz */
{ 16800000, 1600000000, 857, 9, 1, 8 }, /* actual: 1599.7 MHz */
{ 19200000, 1600000000, 500, 6, 1, 8 },
{ 26000000, 1600000000, 800, 13, 1, 8 },
/* 1.5 GHz */
{ 12000000, 1500000000, 750, 6, 0, 8 },
{ 13000000, 1500000000, 923, 8, 0, 8 }, /* actual: 1499.8 MHz */
{ 16800000, 1500000000, 625, 7, 0, 8 },
{ 19200000, 1500000000, 625, 8, 0, 8 },
{ 26000000, 1500000000, 750, 13, 0, 8 },
{ 12000000, 1500000000, 750, 6, 1, 8 },
{ 13000000, 1500000000, 923, 8, 1, 8 }, /* actual: 1499.8 MHz */
{ 16800000, 1500000000, 625, 7, 1, 8 },
{ 19200000, 1500000000, 625, 8, 1, 8 },
{ 26000000, 1500000000, 750, 13, 1, 8 },
/* 1.4 GHz */
{ 12000000, 1400000000, 700, 6, 0, 8 },
{ 13000000, 1400000000, 969, 9, 0, 8 }, /* actual: 1399.7 MHz */
{ 16800000, 1400000000, 1000, 12, 0, 8 },
{ 19200000, 1400000000, 875, 12, 0, 8 },
{ 26000000, 1400000000, 700, 13, 0, 8 },
{ 12000000, 1400000000, 700, 6, 1, 8 },
{ 13000000, 1400000000, 969, 9, 1, 8 }, /* actual: 1399.7 MHz */
{ 16800000, 1400000000, 1000, 12, 1, 8 },
{ 19200000, 1400000000, 875, 12, 1, 8 },
{ 26000000, 1400000000, 700, 13, 1, 8 },
/* 1.3 GHz */
{ 12000000, 1300000000, 975, 9, 0, 8 },
{ 13000000, 1300000000, 1000, 10, 0, 8 },
{ 16800000, 1300000000, 928, 12, 0, 8 }, /* actual: 1299.2 MHz */
{ 19200000, 1300000000, 812, 12, 0, 8 }, /* actual: 1299.2 MHz */
{ 26000000, 1300000000, 650, 13, 0, 8 },
{ 12000000, 1300000000, 975, 9, 1, 8 },
{ 13000000, 1300000000, 1000, 10, 1, 8 },
{ 16800000, 1300000000, 928, 12, 1, 8 }, /* actual: 1299.2 MHz */
{ 19200000, 1300000000, 812, 12, 1, 8 }, /* actual: 1299.2 MHz */
{ 26000000, 1300000000, 650, 13, 1, 8 },
/* 1.2 GHz */
{ 12000000, 1200000000, 1000, 10, 0, 8 },
{ 13000000, 1200000000, 923, 10, 0, 8 }, /* actual: 1199.9 MHz */
{ 16800000, 1200000000, 1000, 14, 0, 8 },
{ 19200000, 1200000000, 1000, 16, 0, 8 },
{ 26000000, 1200000000, 600, 13, 0, 8 },
{ 12000000, 1200000000, 1000, 10, 1, 8 },
{ 13000000, 1200000000, 923, 10, 1, 8 }, /* actual: 1199.9 MHz */
{ 16800000, 1200000000, 1000, 14, 1, 8 },
{ 19200000, 1200000000, 1000, 16, 1, 8 },
{ 26000000, 1200000000, 600, 13, 1, 8 },
/* 1.1 GHz */
{ 12000000, 1100000000, 825, 9, 0, 8 },
{ 13000000, 1100000000, 846, 10, 0, 8 }, /* actual: 1099.8 MHz */
{ 16800000, 1100000000, 982, 15, 0, 8 }, /* actual: 1099.8 MHz */
{ 19200000, 1100000000, 859, 15, 0, 8 }, /* actual: 1099.5 MHz */
{ 26000000, 1100000000, 550, 13, 0, 8 },
{ 12000000, 1100000000, 825, 9, 1, 8 },
{ 13000000, 1100000000, 846, 10, 1, 8 }, /* actual: 1099.8 MHz */
{ 16800000, 1100000000, 982, 15, 1, 8 }, /* actual: 1099.8 MHz */
{ 19200000, 1100000000, 859, 15, 1, 8 }, /* actual: 1099.5 MHz */
{ 26000000, 1100000000, 550, 13, 1, 8 },
/* 1 GHz */
{ 12000000, 1000000000, 1000, 12, 0, 8 },
{ 13000000, 1000000000, 1000, 13, 0, 8 },
{ 16800000, 1000000000, 833, 14, 0, 8 }, /* actual: 999.6 MHz */
{ 19200000, 1000000000, 625, 12, 0, 8 },
{ 26000000, 1000000000, 1000, 26, 0, 8 },
{ 12000000, 1000000000, 1000, 12, 1, 8 },
{ 13000000, 1000000000, 1000, 13, 1, 8 },
{ 16800000, 1000000000, 833, 14, 1, 8 }, /* actual: 999.6 MHz */
{ 19200000, 1000000000, 625, 12, 1, 8 },
{ 26000000, 1000000000, 1000, 26, 1, 8 },
{ 0, 0, 0, 0, 0, 0 },
};
static const struct pdiv_map plle_p[] = {
{ .pdiv = 18, .hw_val = 18 },
{ .pdiv = 24, .hw_val = 24 },
{ .pdiv = 0, .hw_val = 0 },
};
static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
/* PLLE special case: use cpcon field to store cml divider value */
{ 12000000, 100000000, 150, 1, 18, 11 },
@@ -573,6 +579,7 @@ static struct tegra_clk_pll_params pll_e_params = {
.lock_mask = PLLE_MISC_LOCK,
.lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
.lock_delay = 300,
.pdiv_tohw = plle_p,
.freq_table = pll_e_freq_table,
.flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED |
TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC,