[PATCH] powerpc: merge the rest of arch/ppc*/oprofile
- merge common.c - move model specific files - remove stub Makefiles - clean up arch/ppc*/Makefile Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Stephen Rothwell
committed by
Paul Mackerras
Paul Mackerras
parent
654810ec89
commit
86a5cddbd9
214
arch/powerpc/oprofile/common.c
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214
arch/powerpc/oprofile/common.c
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@@ -0,0 +1,214 @@
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/*
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* PPC 64 oprofile support:
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* Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
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* PPC 32 oprofile support: (based on PPC 64 support)
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* Copyright (C) Freescale Semiconductor, Inc 2004
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* Author: Andy Fleming
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*
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* Based on alpha version.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/oprofile.h>
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#ifndef __powerpc64__
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#include <linux/slab.h>
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#endif /* ! __powerpc64__ */
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/errno.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#ifdef __powerpc64__
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#include <asm/pmc.h>
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#else /* __powerpc64__ */
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#include <asm/perfmon.h>
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#endif /* __powerpc64__ */
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#include <asm/cputable.h>
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#include <asm/oprofile_impl.h>
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static struct op_powerpc_model *model;
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static struct op_counter_config ctr[OP_MAX_COUNTER];
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static struct op_system_config sys;
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#ifndef __powerpc64__
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static char *cpu_type;
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#endif /* ! __powerpc64__ */
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static void op_handle_interrupt(struct pt_regs *regs)
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{
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model->handle_interrupt(regs, ctr);
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}
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static int op_powerpc_setup(void)
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{
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#ifdef __powerpc64__
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int err;
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/* Grab the hardware */
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err = reserve_pmc_hardware(op_handle_interrupt);
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if (err)
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return err;
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#else /* __powerpc64__ */
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/* Install our interrupt handler into the existing hook. */
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if (request_perfmon_irq(&op_handle_interrupt))
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return -EBUSY;
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mb();
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#endif /* __powerpc64__ */
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/* Pre-compute the values to stuff in the hardware registers. */
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model->reg_setup(ctr, &sys, model->num_counters);
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/* Configure the registers on all cpus. */
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#ifdef __powerpc64__
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on_each_cpu(model->cpu_setup, NULL, 0, 1);
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#else /* __powerpc64__ */
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#if 0
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/* FIXME: Make multi-cpu work */
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on_each_cpu(model->reg_setup, NULL, 0, 1);
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#endif
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#endif /* __powerpc64__ */
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return 0;
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}
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static void op_powerpc_shutdown(void)
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{
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#ifdef __powerpc64__
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release_pmc_hardware();
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#else /* __powerpc64__ */
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mb();
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/* Remove our interrupt handler. We may be removing this module. */
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free_perfmon_irq();
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#endif /* __powerpc64__ */
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}
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static void op_powerpc_cpu_start(void *dummy)
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{
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model->start(ctr);
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}
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static int op_powerpc_start(void)
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{
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on_each_cpu(op_powerpc_cpu_start, NULL, 0, 1);
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return 0;
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}
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static inline void op_powerpc_cpu_stop(void *dummy)
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{
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model->stop();
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}
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static void op_powerpc_stop(void)
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{
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on_each_cpu(op_powerpc_cpu_stop, NULL, 0, 1);
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}
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static int op_powerpc_create_files(struct super_block *sb, struct dentry *root)
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{
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int i;
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#ifdef __powerpc64__
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/*
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* There is one mmcr0, mmcr1 and mmcra for setting the events for
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* all of the counters.
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*/
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oprofilefs_create_ulong(sb, root, "mmcr0", &sys.mmcr0);
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oprofilefs_create_ulong(sb, root, "mmcr1", &sys.mmcr1);
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oprofilefs_create_ulong(sb, root, "mmcra", &sys.mmcra);
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#endif /* __powerpc64__ */
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for (i = 0; i < model->num_counters; ++i) {
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struct dentry *dir;
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char buf[3];
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snprintf(buf, sizeof buf, "%d", i);
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dir = oprofilefs_mkdir(sb, root, buf);
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oprofilefs_create_ulong(sb, dir, "enabled", &ctr[i].enabled);
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oprofilefs_create_ulong(sb, dir, "event", &ctr[i].event);
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oprofilefs_create_ulong(sb, dir, "count", &ctr[i].count);
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#ifdef __powerpc64__
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/*
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* We dont support per counter user/kernel selection, but
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* we leave the entries because userspace expects them
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*/
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#endif /* __powerpc64__ */
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oprofilefs_create_ulong(sb, dir, "kernel", &ctr[i].kernel);
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oprofilefs_create_ulong(sb, dir, "user", &ctr[i].user);
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#ifndef __powerpc64__
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/* FIXME: Not sure if this is used */
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#endif /* ! __powerpc64__ */
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oprofilefs_create_ulong(sb, dir, "unit_mask", &ctr[i].unit_mask);
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}
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oprofilefs_create_ulong(sb, root, "enable_kernel", &sys.enable_kernel);
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oprofilefs_create_ulong(sb, root, "enable_user", &sys.enable_user);
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#ifdef __powerpc64__
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oprofilefs_create_ulong(sb, root, "backtrace_spinlocks",
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&sys.backtrace_spinlocks);
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#endif /* __powerpc64__ */
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/* Default to tracing both kernel and user */
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sys.enable_kernel = 1;
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sys.enable_user = 1;
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#ifdef __powerpc64__
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/* Turn on backtracing through spinlocks by default */
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sys.backtrace_spinlocks = 1;
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#endif /* __powerpc64__ */
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return 0;
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}
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int __init oprofile_arch_init(struct oprofile_operations *ops)
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{
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#ifndef __powerpc64__
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int cpu_id = smp_processor_id();
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#ifdef CONFIG_FSL_BOOKE
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model = &op_model_fsl_booke;
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#else
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return -ENODEV;
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#endif
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cpu_type = kmalloc(32, GFP_KERNEL);
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if (NULL == cpu_type)
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return -ENOMEM;
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sprintf(cpu_type, "ppc/%s", cur_cpu_spec[cpu_id]->cpu_name);
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model->num_counters = cur_cpu_spec[cpu_id]->num_pmcs;
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ops->cpu_type = cpu_type;
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#else /* __powerpc64__ */
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if (!cur_cpu_spec->oprofile_model || !cur_cpu_spec->oprofile_cpu_type)
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return -ENODEV;
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model = cur_cpu_spec->oprofile_model;
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model->num_counters = cur_cpu_spec->num_pmcs;
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ops->cpu_type = cur_cpu_spec->oprofile_cpu_type;
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#endif /* __powerpc64__ */
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ops->create_files = op_powerpc_create_files;
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ops->setup = op_powerpc_setup;
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ops->shutdown = op_powerpc_shutdown;
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ops->start = op_powerpc_start;
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ops->stop = op_powerpc_stop;
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printk(KERN_INFO "oprofile: using %s performance monitoring.\n",
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ops->cpu_type);
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return 0;
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}
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void oprofile_arch_exit(void)
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{
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#ifndef __powerpc64__
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kfree(cpu_type);
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cpu_type = NULL;
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#endif /* ! __powerpc64__ */
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}
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183
arch/powerpc/oprofile/op_model_fsl_booke.c
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183
arch/powerpc/oprofile/op_model_fsl_booke.c
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@@ -0,0 +1,183 @@
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/*
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* oprofile/op_model_e500.c
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*
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* Freescale Book-E oprofile support, based on ppc64 oprofile support
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* Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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* Copyright (c) 2004 Freescale Semiconductor, Inc
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*
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* Author: Andy Fleming
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* Maintainer: Kumar Gala <Kumar.Gala@freescale.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/oprofile.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#include <asm/processor.h>
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#include <asm/cputable.h>
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#include <asm/reg_booke.h>
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#include <asm/page.h>
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#include <asm/perfmon.h>
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#include <asm/oprofile_impl.h>
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static unsigned long reset_value[OP_MAX_COUNTER];
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static int num_counters;
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static int oprofile_running;
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static inline unsigned int ctr_read(unsigned int i)
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{
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switch(i) {
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case 0:
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return mfpmr(PMRN_PMC0);
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case 1:
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return mfpmr(PMRN_PMC1);
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case 2:
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return mfpmr(PMRN_PMC2);
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case 3:
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return mfpmr(PMRN_PMC3);
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default:
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return 0;
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}
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}
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static inline void ctr_write(unsigned int i, unsigned int val)
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{
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switch(i) {
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case 0:
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mtpmr(PMRN_PMC0, val);
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break;
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case 1:
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mtpmr(PMRN_PMC1, val);
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break;
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case 2:
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mtpmr(PMRN_PMC2, val);
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break;
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case 3:
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mtpmr(PMRN_PMC3, val);
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break;
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default:
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break;
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}
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}
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static void fsl_booke_reg_setup(struct op_counter_config *ctr,
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struct op_system_config *sys,
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int num_ctrs)
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{
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int i;
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num_counters = num_ctrs;
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/* freeze all counters */
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pmc_stop_ctrs();
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/* Our counters count up, and "count" refers to
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* how much before the next interrupt, and we interrupt
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* on overflow. So we calculate the starting value
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* which will give us "count" until overflow.
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* Then we set the events on the enabled counters */
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for (i = 0; i < num_counters; ++i) {
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reset_value[i] = 0x80000000UL - ctr[i].count;
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init_pmc_stop(i);
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set_pmc_event(i, ctr[i].event);
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set_pmc_user_kernel(i, ctr[i].user, ctr[i].kernel);
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}
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}
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static void fsl_booke_start(struct op_counter_config *ctr)
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{
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int i;
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mtmsr(mfmsr() | MSR_PMM);
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for (i = 0; i < num_counters; ++i) {
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if (ctr[i].enabled) {
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ctr_write(i, reset_value[i]);
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/* Set Each enabled counterd to only
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* count when the Mark bit is not set */
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set_pmc_marked(i, 1, 0);
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pmc_start_ctr(i, 1);
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} else {
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ctr_write(i, 0);
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/* Set the ctr to be stopped */
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pmc_start_ctr(i, 0);
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}
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}
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/* Clear the freeze bit, and enable the interrupt.
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* The counters won't actually start until the rfi clears
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* the PMM bit */
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pmc_start_ctrs(1);
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oprofile_running = 1;
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pr_debug("start on cpu %d, pmgc0 %x\n", smp_processor_id(),
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mfpmr(PMRN_PMGC0));
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}
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static void fsl_booke_stop(void)
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{
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/* freeze counters */
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pmc_stop_ctrs();
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oprofile_running = 0;
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pr_debug("stop on cpu %d, pmgc0 %x\n", smp_processor_id(),
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mfpmr(PMRN_PMGC0));
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mb();
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}
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static void fsl_booke_handle_interrupt(struct pt_regs *regs,
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struct op_counter_config *ctr)
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{
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unsigned long pc;
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int is_kernel;
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int val;
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int i;
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/* set the PMM bit (see comment below) */
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mtmsr(mfmsr() | MSR_PMM);
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pc = regs->nip;
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is_kernel = (pc >= KERNELBASE);
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for (i = 0; i < num_counters; ++i) {
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val = ctr_read(i);
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if (val < 0) {
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if (oprofile_running && ctr[i].enabled) {
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oprofile_add_pc(pc, is_kernel, i);
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ctr_write(i, reset_value[i]);
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} else {
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ctr_write(i, 0);
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}
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}
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}
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/* The freeze bit was set by the interrupt. */
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/* Clear the freeze bit, and reenable the interrupt.
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* The counters won't actually start until the rfi clears
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* the PMM bit */
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pmc_start_ctrs(1);
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}
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struct op_powerpc_model op_model_fsl_booke = {
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.reg_setup = fsl_booke_reg_setup,
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.start = fsl_booke_start,
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.stop = fsl_booke_stop,
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.handle_interrupt = fsl_booke_handle_interrupt,
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};
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309
arch/powerpc/oprofile/op_model_power4.c
Normal file
309
arch/powerpc/oprofile/op_model_power4.c
Normal file
@@ -0,0 +1,309 @@
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/*
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* Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
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*
|
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
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* 2 of the License, or (at your option) any later version.
|
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*/
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#include <linux/oprofile.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#include <asm/processor.h>
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#include <asm/cputable.h>
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#include <asm/systemcfg.h>
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#include <asm/rtas.h>
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#include <asm/oprofile_impl.h>
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#define dbg(args...)
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static unsigned long reset_value[OP_MAX_COUNTER];
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static int oprofile_running;
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static int mmcra_has_sihv;
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/* mmcr values are set in power4_reg_setup, used in power4_cpu_setup */
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static u32 mmcr0_val;
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static u64 mmcr1_val;
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static u32 mmcra_val;
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/*
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* Since we do not have an NMI, backtracing through spinlocks is
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* only a best guess. In light of this, allow it to be disabled at
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* runtime.
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*/
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static int backtrace_spinlocks;
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static void power4_reg_setup(struct op_counter_config *ctr,
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struct op_system_config *sys,
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int num_ctrs)
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{
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int i;
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/*
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* SIHV / SIPR bits are only implemented on POWER4+ (GQ) and above.
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* However we disable it on all POWER4 until we verify it works
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* (I was seeing some strange behaviour last time I tried).
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*
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* It has been verified to work on POWER5 so we enable it there.
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*/
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if (cpu_has_feature(CPU_FTR_MMCRA_SIHV))
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mmcra_has_sihv = 1;
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/*
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* The performance counter event settings are given in the mmcr0,
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* mmcr1 and mmcra values passed from the user in the
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* op_system_config structure (sys variable).
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*/
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mmcr0_val = sys->mmcr0;
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mmcr1_val = sys->mmcr1;
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mmcra_val = sys->mmcra;
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backtrace_spinlocks = sys->backtrace_spinlocks;
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for (i = 0; i < cur_cpu_spec->num_pmcs; ++i)
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reset_value[i] = 0x80000000UL - ctr[i].count;
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/* setup user and kernel profiling */
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if (sys->enable_kernel)
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mmcr0_val &= ~MMCR0_KERNEL_DISABLE;
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else
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mmcr0_val |= MMCR0_KERNEL_DISABLE;
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if (sys->enable_user)
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mmcr0_val &= ~MMCR0_PROBLEM_DISABLE;
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else
|
||||
mmcr0_val |= MMCR0_PROBLEM_DISABLE;
|
||||
}
|
||||
|
||||
extern void ppc64_enable_pmcs(void);
|
||||
|
||||
static void power4_cpu_setup(void *unused)
|
||||
{
|
||||
unsigned int mmcr0 = mmcr0_val;
|
||||
unsigned long mmcra = mmcra_val;
|
||||
|
||||
ppc64_enable_pmcs();
|
||||
|
||||
/* set the freeze bit */
|
||||
mmcr0 |= MMCR0_FC;
|
||||
mtspr(SPRN_MMCR0, mmcr0);
|
||||
|
||||
mmcr0 |= MMCR0_FCM1|MMCR0_PMXE|MMCR0_FCECE;
|
||||
mmcr0 |= MMCR0_PMC1CE|MMCR0_PMCjCE;
|
||||
mtspr(SPRN_MMCR0, mmcr0);
|
||||
|
||||
mtspr(SPRN_MMCR1, mmcr1_val);
|
||||
|
||||
mmcra |= MMCRA_SAMPLE_ENABLE;
|
||||
mtspr(SPRN_MMCRA, mmcra);
|
||||
|
||||
dbg("setup on cpu %d, mmcr0 %lx\n", smp_processor_id(),
|
||||
mfspr(SPRN_MMCR0));
|
||||
dbg("setup on cpu %d, mmcr1 %lx\n", smp_processor_id(),
|
||||
mfspr(SPRN_MMCR1));
|
||||
dbg("setup on cpu %d, mmcra %lx\n", smp_processor_id(),
|
||||
mfspr(SPRN_MMCRA));
|
||||
}
|
||||
|
||||
static void power4_start(struct op_counter_config *ctr)
|
||||
{
|
||||
int i;
|
||||
unsigned int mmcr0;
|
||||
|
||||
/* set the PMM bit (see comment below) */
|
||||
mtmsrd(mfmsr() | MSR_PMM);
|
||||
|
||||
for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
|
||||
if (ctr[i].enabled) {
|
||||
ctr_write(i, reset_value[i]);
|
||||
} else {
|
||||
ctr_write(i, 0);
|
||||
}
|
||||
}
|
||||
|
||||
mmcr0 = mfspr(SPRN_MMCR0);
|
||||
|
||||
/*
|
||||
* We must clear the PMAO bit on some (GQ) chips. Just do it
|
||||
* all the time
|
||||
*/
|
||||
mmcr0 &= ~MMCR0_PMAO;
|
||||
|
||||
/*
|
||||
* now clear the freeze bit, counting will not start until we
|
||||
* rfid from this excetion, because only at that point will
|
||||
* the PMM bit be cleared
|
||||
*/
|
||||
mmcr0 &= ~MMCR0_FC;
|
||||
mtspr(SPRN_MMCR0, mmcr0);
|
||||
|
||||
oprofile_running = 1;
|
||||
|
||||
dbg("start on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
|
||||
}
|
||||
|
||||
static void power4_stop(void)
|
||||
{
|
||||
unsigned int mmcr0;
|
||||
|
||||
/* freeze counters */
|
||||
mmcr0 = mfspr(SPRN_MMCR0);
|
||||
mmcr0 |= MMCR0_FC;
|
||||
mtspr(SPRN_MMCR0, mmcr0);
|
||||
|
||||
oprofile_running = 0;
|
||||
|
||||
dbg("stop on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
|
||||
|
||||
mb();
|
||||
}
|
||||
|
||||
/* Fake functions used by canonicalize_pc */
|
||||
static void __attribute_used__ hypervisor_bucket(void)
|
||||
{
|
||||
}
|
||||
|
||||
static void __attribute_used__ rtas_bucket(void)
|
||||
{
|
||||
}
|
||||
|
||||
static void __attribute_used__ kernel_unknown_bucket(void)
|
||||
{
|
||||
}
|
||||
|
||||
static unsigned long check_spinlock_pc(struct pt_regs *regs,
|
||||
unsigned long profile_pc)
|
||||
{
|
||||
unsigned long pc = instruction_pointer(regs);
|
||||
|
||||
/*
|
||||
* If both the SIAR (sampled instruction) and the perfmon exception
|
||||
* occurred in a spinlock region then we account the sample to the
|
||||
* calling function. This isnt 100% correct, we really need soft
|
||||
* IRQ disable so we always get the perfmon exception at the
|
||||
* point at which the SIAR is set.
|
||||
*/
|
||||
if (backtrace_spinlocks && in_lock_functions(pc) &&
|
||||
in_lock_functions(profile_pc))
|
||||
return regs->link;
|
||||
else
|
||||
return profile_pc;
|
||||
}
|
||||
|
||||
/*
|
||||
* On GQ and newer the MMCRA stores the HV and PR bits at the time
|
||||
* the SIAR was sampled. We use that to work out if the SIAR was sampled in
|
||||
* the hypervisor, our exception vectors or RTAS.
|
||||
*/
|
||||
static unsigned long get_pc(struct pt_regs *regs)
|
||||
{
|
||||
unsigned long pc = mfspr(SPRN_SIAR);
|
||||
unsigned long mmcra;
|
||||
|
||||
/* Cant do much about it */
|
||||
if (!mmcra_has_sihv)
|
||||
return check_spinlock_pc(regs, pc);
|
||||
|
||||
mmcra = mfspr(SPRN_MMCRA);
|
||||
|
||||
/* Were we in the hypervisor? */
|
||||
if ((systemcfg->platform == PLATFORM_PSERIES_LPAR) &&
|
||||
(mmcra & MMCRA_SIHV))
|
||||
/* function descriptor madness */
|
||||
return *((unsigned long *)hypervisor_bucket);
|
||||
|
||||
/* We were in userspace, nothing to do */
|
||||
if (mmcra & MMCRA_SIPR)
|
||||
return pc;
|
||||
|
||||
#ifdef CONFIG_PPC_RTAS
|
||||
/* Were we in RTAS? */
|
||||
if (pc >= rtas.base && pc < (rtas.base + rtas.size))
|
||||
/* function descriptor madness */
|
||||
return *((unsigned long *)rtas_bucket);
|
||||
#endif
|
||||
|
||||
/* Were we in our exception vectors or SLB real mode miss handler? */
|
||||
if (pc < 0x1000000UL)
|
||||
return (unsigned long)__va(pc);
|
||||
|
||||
/* Not sure where we were */
|
||||
if (pc < KERNELBASE)
|
||||
/* function descriptor madness */
|
||||
return *((unsigned long *)kernel_unknown_bucket);
|
||||
|
||||
return check_spinlock_pc(regs, pc);
|
||||
}
|
||||
|
||||
static int get_kernel(unsigned long pc)
|
||||
{
|
||||
int is_kernel;
|
||||
|
||||
if (!mmcra_has_sihv) {
|
||||
is_kernel = (pc >= KERNELBASE);
|
||||
} else {
|
||||
unsigned long mmcra = mfspr(SPRN_MMCRA);
|
||||
is_kernel = ((mmcra & MMCRA_SIPR) == 0);
|
||||
}
|
||||
|
||||
return is_kernel;
|
||||
}
|
||||
|
||||
static void power4_handle_interrupt(struct pt_regs *regs,
|
||||
struct op_counter_config *ctr)
|
||||
{
|
||||
unsigned long pc;
|
||||
int is_kernel;
|
||||
int val;
|
||||
int i;
|
||||
unsigned int mmcr0;
|
||||
|
||||
pc = get_pc(regs);
|
||||
is_kernel = get_kernel(pc);
|
||||
|
||||
/* set the PMM bit (see comment below) */
|
||||
mtmsrd(mfmsr() | MSR_PMM);
|
||||
|
||||
for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
|
||||
val = ctr_read(i);
|
||||
if (val < 0) {
|
||||
if (oprofile_running && ctr[i].enabled) {
|
||||
oprofile_add_pc(pc, is_kernel, i);
|
||||
ctr_write(i, reset_value[i]);
|
||||
} else {
|
||||
ctr_write(i, 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
mmcr0 = mfspr(SPRN_MMCR0);
|
||||
|
||||
/* reset the perfmon trigger */
|
||||
mmcr0 |= MMCR0_PMXE;
|
||||
|
||||
/*
|
||||
* We must clear the PMAO bit on some (GQ) chips. Just do it
|
||||
* all the time
|
||||
*/
|
||||
mmcr0 &= ~MMCR0_PMAO;
|
||||
|
||||
/*
|
||||
* now clear the freeze bit, counting will not start until we
|
||||
* rfid from this exception, because only at that point will
|
||||
* the PMM bit be cleared
|
||||
*/
|
||||
mmcr0 &= ~MMCR0_FC;
|
||||
mtspr(SPRN_MMCR0, mmcr0);
|
||||
}
|
||||
|
||||
struct op_powerpc_model op_model_power4 = {
|
||||
.reg_setup = power4_reg_setup,
|
||||
.cpu_setup = power4_cpu_setup,
|
||||
.start = power4_start,
|
||||
.stop = power4_stop,
|
||||
.handle_interrupt = power4_handle_interrupt,
|
||||
};
|
||||
218
arch/powerpc/oprofile/op_model_rs64.c
Normal file
218
arch/powerpc/oprofile/op_model_rs64.c
Normal file
@@ -0,0 +1,218 @@
|
||||
/*
|
||||
* Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/oprofile.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/smp.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/cputable.h>
|
||||
#include <asm/oprofile_impl.h>
|
||||
|
||||
#define dbg(args...)
|
||||
|
||||
static void ctrl_write(unsigned int i, unsigned int val)
|
||||
{
|
||||
unsigned int tmp = 0;
|
||||
unsigned long shift = 0, mask = 0;
|
||||
|
||||
dbg("ctrl_write %d %x\n", i, val);
|
||||
|
||||
switch(i) {
|
||||
case 0:
|
||||
tmp = mfspr(SPRN_MMCR0);
|
||||
shift = 6;
|
||||
mask = 0x7F;
|
||||
break;
|
||||
case 1:
|
||||
tmp = mfspr(SPRN_MMCR0);
|
||||
shift = 0;
|
||||
mask = 0x3F;
|
||||
break;
|
||||
case 2:
|
||||
tmp = mfspr(SPRN_MMCR1);
|
||||
shift = 31 - 4;
|
||||
mask = 0x1F;
|
||||
break;
|
||||
case 3:
|
||||
tmp = mfspr(SPRN_MMCR1);
|
||||
shift = 31 - 9;
|
||||
mask = 0x1F;
|
||||
break;
|
||||
case 4:
|
||||
tmp = mfspr(SPRN_MMCR1);
|
||||
shift = 31 - 14;
|
||||
mask = 0x1F;
|
||||
break;
|
||||
case 5:
|
||||
tmp = mfspr(SPRN_MMCR1);
|
||||
shift = 31 - 19;
|
||||
mask = 0x1F;
|
||||
break;
|
||||
case 6:
|
||||
tmp = mfspr(SPRN_MMCR1);
|
||||
shift = 31 - 24;
|
||||
mask = 0x1F;
|
||||
break;
|
||||
case 7:
|
||||
tmp = mfspr(SPRN_MMCR1);
|
||||
shift = 31 - 28;
|
||||
mask = 0xF;
|
||||
break;
|
||||
}
|
||||
|
||||
tmp = tmp & ~(mask << shift);
|
||||
tmp |= val << shift;
|
||||
|
||||
switch(i) {
|
||||
case 0:
|
||||
case 1:
|
||||
mtspr(SPRN_MMCR0, tmp);
|
||||
break;
|
||||
default:
|
||||
mtspr(SPRN_MMCR1, tmp);
|
||||
}
|
||||
|
||||
dbg("ctrl_write mmcr0 %lx mmcr1 %lx\n", mfspr(SPRN_MMCR0),
|
||||
mfspr(SPRN_MMCR1));
|
||||
}
|
||||
|
||||
static unsigned long reset_value[OP_MAX_COUNTER];
|
||||
|
||||
static int num_counters;
|
||||
|
||||
static void rs64_reg_setup(struct op_counter_config *ctr,
|
||||
struct op_system_config *sys,
|
||||
int num_ctrs)
|
||||
{
|
||||
int i;
|
||||
|
||||
num_counters = num_ctrs;
|
||||
|
||||
for (i = 0; i < num_counters; ++i)
|
||||
reset_value[i] = 0x80000000UL - ctr[i].count;
|
||||
|
||||
/* XXX setup user and kernel profiling */
|
||||
}
|
||||
|
||||
static void rs64_cpu_setup(void *unused)
|
||||
{
|
||||
unsigned int mmcr0;
|
||||
|
||||
/* reset MMCR0 and set the freeze bit */
|
||||
mmcr0 = MMCR0_FC;
|
||||
mtspr(SPRN_MMCR0, mmcr0);
|
||||
|
||||
/* reset MMCR1, MMCRA */
|
||||
mtspr(SPRN_MMCR1, 0);
|
||||
|
||||
if (cpu_has_feature(CPU_FTR_MMCRA))
|
||||
mtspr(SPRN_MMCRA, 0);
|
||||
|
||||
mmcr0 |= MMCR0_FCM1|MMCR0_PMXE|MMCR0_FCECE;
|
||||
/* Only applies to POWER3, but should be safe on RS64 */
|
||||
mmcr0 |= MMCR0_PMC1CE|MMCR0_PMCjCE;
|
||||
mtspr(SPRN_MMCR0, mmcr0);
|
||||
|
||||
dbg("setup on cpu %d, mmcr0 %lx\n", smp_processor_id(),
|
||||
mfspr(SPRN_MMCR0));
|
||||
dbg("setup on cpu %d, mmcr1 %lx\n", smp_processor_id(),
|
||||
mfspr(SPRN_MMCR1));
|
||||
}
|
||||
|
||||
static void rs64_start(struct op_counter_config *ctr)
|
||||
{
|
||||
int i;
|
||||
unsigned int mmcr0;
|
||||
|
||||
/* set the PMM bit (see comment below) */
|
||||
mtmsrd(mfmsr() | MSR_PMM);
|
||||
|
||||
for (i = 0; i < num_counters; ++i) {
|
||||
if (ctr[i].enabled) {
|
||||
ctr_write(i, reset_value[i]);
|
||||
ctrl_write(i, ctr[i].event);
|
||||
} else {
|
||||
ctr_write(i, 0);
|
||||
}
|
||||
}
|
||||
|
||||
mmcr0 = mfspr(SPRN_MMCR0);
|
||||
|
||||
/*
|
||||
* now clear the freeze bit, counting will not start until we
|
||||
* rfid from this excetion, because only at that point will
|
||||
* the PMM bit be cleared
|
||||
*/
|
||||
mmcr0 &= ~MMCR0_FC;
|
||||
mtspr(SPRN_MMCR0, mmcr0);
|
||||
|
||||
dbg("start on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
|
||||
}
|
||||
|
||||
static void rs64_stop(void)
|
||||
{
|
||||
unsigned int mmcr0;
|
||||
|
||||
/* freeze counters */
|
||||
mmcr0 = mfspr(SPRN_MMCR0);
|
||||
mmcr0 |= MMCR0_FC;
|
||||
mtspr(SPRN_MMCR0, mmcr0);
|
||||
|
||||
dbg("stop on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
|
||||
|
||||
mb();
|
||||
}
|
||||
|
||||
static void rs64_handle_interrupt(struct pt_regs *regs,
|
||||
struct op_counter_config *ctr)
|
||||
{
|
||||
unsigned int mmcr0;
|
||||
int val;
|
||||
int i;
|
||||
unsigned long pc = mfspr(SPRN_SIAR);
|
||||
int is_kernel = (pc >= KERNELBASE);
|
||||
|
||||
/* set the PMM bit (see comment below) */
|
||||
mtmsrd(mfmsr() | MSR_PMM);
|
||||
|
||||
for (i = 0; i < num_counters; ++i) {
|
||||
val = ctr_read(i);
|
||||
if (val < 0) {
|
||||
if (ctr[i].enabled) {
|
||||
oprofile_add_pc(pc, is_kernel, i);
|
||||
ctr_write(i, reset_value[i]);
|
||||
} else {
|
||||
ctr_write(i, 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
mmcr0 = mfspr(SPRN_MMCR0);
|
||||
|
||||
/* reset the perfmon trigger */
|
||||
mmcr0 |= MMCR0_PMXE;
|
||||
|
||||
/*
|
||||
* now clear the freeze bit, counting will not start until we
|
||||
* rfid from this exception, because only at that point will
|
||||
* the PMM bit be cleared
|
||||
*/
|
||||
mmcr0 &= ~MMCR0_FC;
|
||||
mtspr(SPRN_MMCR0, mmcr0);
|
||||
}
|
||||
|
||||
struct op_powerpc_model op_model_rs64 = {
|
||||
.reg_setup = rs64_reg_setup,
|
||||
.cpu_setup = rs64_cpu_setup,
|
||||
.start = rs64_start,
|
||||
.stop = rs64_stop,
|
||||
.handle_interrupt = rs64_handle_interrupt,
|
||||
};
|
||||
Reference in New Issue
Block a user