Merge branch 'edp-training-fixes' into drm-intel-next
Conflicts: drivers/gpu/drm/i915/intel_dp.c Just whitespace change conflicts
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@@ -1777,6 +1777,26 @@ static void ironlake_irq_preinstall(struct drm_device *dev)
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POSTING_READ(SDEIER);
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}
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/*
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* Enable digital hotplug on the PCH, and configure the DP short pulse
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* duration to 2ms (which is the minimum in the Display Port spec)
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*
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* This register is the same on all known PCH chips.
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*/
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static void ironlake_enable_pch_hotplug(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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u32 hotplug;
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hotplug = I915_READ(PCH_PORT_HOTPLUG);
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hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
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hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
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hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
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hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
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I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
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}
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static int ironlake_irq_postinstall(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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@@ -1839,6 +1859,8 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
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I915_WRITE(SDEIER, hotplug_mask);
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POSTING_READ(SDEIER);
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ironlake_enable_pch_hotplug(dev);
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if (IS_IRONLAKE_M(dev)) {
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/* Clear & enable PCU event interrupts */
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I915_WRITE(DEIIR, DE_PCU_EVENT);
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@@ -1896,6 +1918,8 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
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I915_WRITE(SDEIER, hotplug_mask);
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POSTING_READ(SDEIER);
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ironlake_enable_pch_hotplug(dev);
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return 0;
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}
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@@ -2020,6 +2044,10 @@ static void ironlake_irq_uninstall(struct drm_device *dev)
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I915_WRITE(GTIMR, 0xffffffff);
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I915_WRITE(GTIER, 0x0);
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I915_WRITE(GTIIR, I915_READ(GTIIR));
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I915_WRITE(SDEIMR, 0xffffffff);
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I915_WRITE(SDEIER, 0x0);
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I915_WRITE(SDEIIR, I915_READ(SDEIIR));
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}
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static void i915_driver_irq_uninstall(struct drm_device * dev)
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