drm/radeon/cik: restructure rlc setup
Restructure rlc setup to handle clock and power gating. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@@ -905,6 +905,7 @@
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#define RLC_LB_CNTR_MAX 0xC348
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#define RLC_LB_CNTL 0xC364
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# define LOAD_BALANCE_ENABLE (1 << 0)
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#define RLC_LB_CNTR_INIT 0xC36C
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