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MIPS: Netlogic: SYS block updates of XLP9XX

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Add the SYS block registers for XLP9XX, most of them have changed.
The wakeup sequence has been updated to set the coherent mode from
the main thread rather than the woken up thread.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6280/
This commit is contained in:
Jayachandran C
2013-12-21 16:52:23 +05:30
committed by Ralf Baechle
parent d150cef4e8
commit 861c056953
5 changed files with 86 additions and 28 deletions
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8
arch/mips/netlogic/common/reset.S
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@@ -159,6 +159,13 @@ FEXPORT(nlm_reset_entry)
nop
1: /* Entry point on core wakeup */
mfc0 t0, CP0_EBASE, 0 /* processor ID */
andi t0, 0xff00
li t1, 0x1500 /* XLP 9xx */
beq t0, t1, 2f /* does not need to set coherent */
nop
/* set bit in SYS coherent register for the core */
mfc0 t0, CP0_EBASE, 1
mfc0 t1, CP0_EBASE, 1
srl t1, 5
@@ -180,6 +187,7 @@ FEXPORT(nlm_reset_entry)
lw t1, 0(t2)
sync
2:
/* Configure LSU on Non-0 Cores. */
xlp_config_lsu
/* FALL THROUGH */