xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

drm/i915/gt: Eliminate the trylock for reading a timeline's hwsp

Browse Source 
As we stash a pointer to the HWSP cacheline on the request, when reading
it we only need confirm that the cacheline is still valid by checking
that the request and timeline are still intact.

v2: Protect hwsp_cachline with RCU

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191217011659.3092130-1-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
2019-12-17 01:16:59 +00:00
parent e14177f197
commit 85bedbf191
4 changed files with 40 additions and 47 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/drm/i915/i915_request.h
View File

@@ -30,6 +30,7 @@
#include "gt/intel_context_types.h"
#include "gt/intel_engine_types.h"
#include "gt/intel_timeline_types.h"
#include "i915_gem.h"
#include "i915_scheduler.h"
@@ -41,8 +42,6 @@
struct drm_file;
struct drm_i915_gem_object;
struct i915_request;
struct intel_timeline;
struct intel_timeline_cacheline;
struct i915_capture_list {
struct i915_capture_list *next;
@@ -183,7 +182,7 @@ struct i915_request {
* inside the timeline's HWSP vma, but it is only valid while this
* request has not completed and guarded by the timeline mutex.
*/
struct intel_timeline_cacheline *hwsp_cacheline;
struct intel_timeline_cacheline __rcu *hwsp_cacheline;
/** Position in the ring of the start of the request */
u32 head;