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[SPARC64]: Niagara copy/clear page.

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Happily we have no D-cache aliasing issues on these
chips, so the implementation is very straightforward.

Add a stub in bootup which will be where the patching
calls will be made for niagara/sun4v/hypervisor.

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
2006-02-07 16:09:12 -08:00
parent df7d6aec96
commit 8591e30272
3 changed files with 114 additions and 0 deletions
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18
arch/sparc64/kernel/head.S
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@@ -316,6 +316,24 @@ sun4u_init:
ba,pt %xcc, spitfire_tlb_fixup
nop
/* XXX Nothing branches to here yet, when %ver register indicates
* XXX Niagara we should do this.
*/
niagara_tlb_fixup:
mov 3, %g2 /* Set TLB type to hypervisor. */
sethi %hi(tlb_type), %g1
stw %g2, [%g1 + %lo(tlb_type)]
/* Patch copy/clear ops. */
call niagara_patch_copyops
nop
call niagara_patch_pageops
nop
/* Patch TLB/cache ops. */
call hypervisor_patch_cachetlbops
nop
cheetah_tlb_fixup:
mov 2, %g2 /* Set TLB type to cheetah+. */
BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)