Merge tag 'pci-v4.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI updates from Bjorn Helgaas: - add framework for supporting PCIe devices in Endpoint mode (Kishon Vijay Abraham I) - use non-postable PCI config space mappings when possible (Lorenzo Pieralisi) - clean up and unify mmap of PCI BARs (David Woodhouse) - export and unify Function Level Reset support (Christoph Hellwig) - avoid FLR for Intel 82579 NICs (Sasha Neftin) - add pci_request_irq() and pci_free_irq() helpers (Christoph Hellwig) - short-circuit config access failures for disconnected devices (Keith Busch) - remove D3 sleep delay when possible (Adrian Hunter) - freeze PME scan before suspending devices (Lukas Wunner) - stop disabling MSI/MSI-X in pci_device_shutdown() (Prarit Bhargava) - disable boot interrupt quirk for ASUS M2N-LR (Stefan Assmann) - add arch-specific alignment control to improve device passthrough by avoiding multiple BARs in a page (Yongji Xie) - add sysfs sriov_drivers_autoprobe to control VF driver binding (Bodong Wang) - allow slots below PCI-to-PCIe "reverse bridges" (Bjorn Helgaas) - fix crashes when unbinding host controllers that don't support removal (Brian Norris) - add driver for MicroSemi Switchtec management interface (Logan Gunthorpe) - add driver for Faraday Technology FTPCI100 host bridge (Linus Walleij) - add i.MX7D support (Andrey Smirnov) - use generic MSI support for Aardvark (Thomas Petazzoni) - make Rockchip driver modular (Brian Norris) - advertise 128-byte Read Completion Boundary support for Rockchip (Shawn Lin) - advertise PCI_EXP_LNKSTA_SLC for Rockchip root port (Shawn Lin) - convert atomic_t to refcount_t in HV driver (Elena Reshetova) - add CPU IRQ affinity in HV driver (K. Y. Srinivasan) - fix PCI bus removal in HV driver (Long Li) - add support for ThunderX2 DMA alias topology (Jayachandran C) - add ThunderX pass2.x 2nd node MCFG quirk (Tomasz Nowicki) - add ITE 8893 bridge DMA alias quirk (Jarod Wilson) - restrict Cavium ACS quirk only to CN81xx/CN83xx/CN88xx devices (Manish Jaggi) * tag 'pci-v4.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (146 commits) PCI: Don't allow unbinding host controllers that aren't prepared ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP MAINTAINERS: Add PCI Endpoint maintainer Documentation: PCI: Add userguide for PCI endpoint test function tools: PCI: Add sample test script to invoke pcitest tools: PCI: Add a userspace tool to test PCI endpoint Documentation: misc-devices: Add Documentation for pci-endpoint-test driver misc: Add host side PCI driver for PCI test function device PCI: Add device IDs for DRA74x and DRA72x dt-bindings: PCI: dra7xx: Add DT bindings to enable unaligned access PCI: dwc: dra7xx: Workaround for errata id i870 dt-bindings: PCI: dra7xx: Add DT bindings for PCI dra7xx EP mode PCI: dwc: dra7xx: Add EP mode support PCI: dwc: dra7xx: Facilitate wrapper and MSI interrupts to be enabled independently dt-bindings: PCI: Add DT bindings for PCI designware EP mode PCI: dwc: designware: Add EP mode support Documentation: PCI: Add binding documentation for pci-test endpoint function ixgbe: Use pcie_flr() instead of duplicating it IB/hfi1: Use pcie_flr() instead of duplicating it PCI: imx6: Fix spelling mistake: "contol" -> "control" ...
This commit is contained in:
Linus Torvalds
@@ -155,7 +155,7 @@ extern int __must_check
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request_percpu_irq(unsigned int irq, irq_handler_t handler,
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const char *devname, void __percpu *percpu_dev_id);
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extern void free_irq(unsigned int, void *);
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extern const void *free_irq(unsigned int, void *);
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extern void free_percpu_irq(unsigned int, void __percpu *);
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struct device;
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@@ -90,6 +90,27 @@ void devm_memunmap(struct device *dev, void *addr);
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void *__devm_memremap_pages(struct device *dev, struct resource *res);
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#ifdef CONFIG_PCI
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/*
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* The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and
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* Posting") mandate non-posted configuration transactions. There is
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* no ioremap API in the kernel that can guarantee non-posted write
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* semantics across arches so provide a default implementation for
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* mapping PCI config space that defaults to ioremap_nocache(); arches
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* should override it if they have memory mapping implementations that
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* guarantee non-posted writes semantics to make the memory mapping
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* compliant with the PCI specification.
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*/
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#ifndef pci_remap_cfgspace
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#define pci_remap_cfgspace pci_remap_cfgspace
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static inline void __iomem *pci_remap_cfgspace(phys_addr_t offset,
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size_t size)
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{
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return ioremap_nocache(offset, size);
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}
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#endif
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#endif
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/*
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* Some systems do not have legacy ISA devices.
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* /dev/port is not a valid interface on these systems.
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@@ -44,4 +44,8 @@
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#define IMX7D_GPR5_CSI_MUX_CONTROL_MIPI (0x1 << 4)
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#define IMX7D_GPR12_PCIE_PHY_REFCLK_SEL BIT(5)
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#define IMX7D_GPR22_PCIE_PHY_PLL_LOCKED BIT(31)
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#endif /* __LINUX_IMX7_IOMUXC_GPR_H */
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@@ -428,6 +428,16 @@ struct i2c_device_id {
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kernel_ulong_t driver_data; /* Data private to the driver */
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};
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/* pci_epf */
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#define PCI_EPF_NAME_SIZE 20
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#define PCI_EPF_MODULE_PREFIX "pci_epf:"
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struct pci_epf_device_id {
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char name[PCI_EPF_NAME_SIZE];
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kernel_ulong_t driver_data;
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};
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/* spi */
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#define SPI_NAME_SIZE 32
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@@ -85,15 +85,4 @@ static inline int of_pci_get_host_bridge_resources(struct device_node *dev,
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}
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#endif
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#if defined(CONFIG_OF) && defined(CONFIG_PCI_MSI)
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int of_pci_msi_chip_add(struct msi_controller *chip);
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void of_pci_msi_chip_remove(struct msi_controller *chip);
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struct msi_controller *of_pci_find_msi_chip_by_node(struct device_node *of_node);
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#else
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static inline int of_pci_msi_chip_add(struct msi_controller *chip) { return -EINVAL; }
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static inline void of_pci_msi_chip_remove(struct msi_controller *chip) { }
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static inline struct msi_controller *
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of_pci_find_msi_chip_by_node(struct device_node *of_node) { return NULL; }
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#endif
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#endif
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@@ -16,6 +16,7 @@
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#ifndef DRIVERS_PCI_ECAM_H
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#define DRIVERS_PCI_ECAM_H
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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@@ -68,7 +69,7 @@ extern struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 */
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extern struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */
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#endif
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#ifdef CONFIG_PCI_HOST_GENERIC
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#ifdef CONFIG_PCI_HOST_COMMON
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/* for DT-based PCI controllers that support ECAM */
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int pci_host_common_probe(struct platform_device *pdev,
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struct pci_ecam_ops *ops);
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41
include/linux/pci-ep-cfs.h
Normal file
41
include/linux/pci-ep-cfs.h
Normal file
@@ -0,0 +1,41 @@
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/**
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* PCI Endpoint ConfigFS header file
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*
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* Copyright (C) 2017 Texas Instruments
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* Author: Kishon Vijay Abraham I <kishon@ti.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 of
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* the License as published by the Free Software Foundation.
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*/
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#ifndef __LINUX_PCI_EP_CFS_H
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#define __LINUX_PCI_EP_CFS_H
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#include <linux/configfs.h>
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#ifdef CONFIG_PCI_ENDPOINT_CONFIGFS
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struct config_group *pci_ep_cfs_add_epc_group(const char *name);
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void pci_ep_cfs_remove_epc_group(struct config_group *group);
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struct config_group *pci_ep_cfs_add_epf_group(const char *name);
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void pci_ep_cfs_remove_epf_group(struct config_group *group);
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#else
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static inline struct config_group *pci_ep_cfs_add_epc_group(const char *name)
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{
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return 0;
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}
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static inline void pci_ep_cfs_remove_epc_group(struct config_group *group)
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{
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}
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static inline struct config_group *pci_ep_cfs_add_epf_group(const char *name)
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{
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return 0;
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}
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static inline void pci_ep_cfs_remove_epf_group(struct config_group *group)
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{
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}
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#endif
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#endif /* __LINUX_PCI_EP_CFS_H */
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144
include/linux/pci-epc.h
Normal file
144
include/linux/pci-epc.h
Normal file
@@ -0,0 +1,144 @@
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/**
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* PCI Endpoint *Controller* (EPC) header file
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*
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* Copyright (C) 2017 Texas Instruments
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* Author: Kishon Vijay Abraham I <kishon@ti.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 of
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* the License as published by the Free Software Foundation.
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*/
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#ifndef __LINUX_PCI_EPC_H
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#define __LINUX_PCI_EPC_H
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#include <linux/pci-epf.h>
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struct pci_epc;
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enum pci_epc_irq_type {
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PCI_EPC_IRQ_UNKNOWN,
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PCI_EPC_IRQ_LEGACY,
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PCI_EPC_IRQ_MSI,
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};
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/**
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* struct pci_epc_ops - set of function pointers for performing EPC operations
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* @write_header: ops to populate configuration space header
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* @set_bar: ops to configure the BAR
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* @clear_bar: ops to reset the BAR
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* @map_addr: ops to map CPU address to PCI address
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* @unmap_addr: ops to unmap CPU address and PCI address
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* @set_msi: ops to set the requested number of MSI interrupts in the MSI
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* capability register
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* @get_msi: ops to get the number of MSI interrupts allocated by the RC from
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* the MSI capability register
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* @raise_irq: ops to raise a legacy or MSI interrupt
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* @start: ops to start the PCI link
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* @stop: ops to stop the PCI link
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* @owner: the module owner containing the ops
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*/
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struct pci_epc_ops {
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int (*write_header)(struct pci_epc *pci_epc,
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struct pci_epf_header *hdr);
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int (*set_bar)(struct pci_epc *epc, enum pci_barno bar,
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dma_addr_t bar_phys, size_t size, int flags);
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void (*clear_bar)(struct pci_epc *epc, enum pci_barno bar);
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int (*map_addr)(struct pci_epc *epc, phys_addr_t addr,
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u64 pci_addr, size_t size);
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void (*unmap_addr)(struct pci_epc *epc, phys_addr_t addr);
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int (*set_msi)(struct pci_epc *epc, u8 interrupts);
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int (*get_msi)(struct pci_epc *epc);
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int (*raise_irq)(struct pci_epc *pci_epc,
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enum pci_epc_irq_type type, u8 interrupt_num);
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int (*start)(struct pci_epc *epc);
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void (*stop)(struct pci_epc *epc);
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struct module *owner;
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};
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/**
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* struct pci_epc_mem - address space of the endpoint controller
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* @phys_base: physical base address of the PCI address space
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* @size: the size of the PCI address space
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* @bitmap: bitmap to manage the PCI address space
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* @pages: number of bits representing the address region
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*/
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struct pci_epc_mem {
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phys_addr_t phys_base;
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size_t size;
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unsigned long *bitmap;
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int pages;
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};
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/**
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* struct pci_epc - represents the PCI EPC device
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* @dev: PCI EPC device
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* @pci_epf: list of endpoint functions present in this EPC device
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* @ops: function pointers for performing endpoint operations
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* @mem: address space of the endpoint controller
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* @max_functions: max number of functions that can be configured in this EPC
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* @group: configfs group representing the PCI EPC device
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* @lock: spinlock to protect pci_epc ops
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*/
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struct pci_epc {
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struct device dev;
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struct list_head pci_epf;
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const struct pci_epc_ops *ops;
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struct pci_epc_mem *mem;
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u8 max_functions;
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struct config_group *group;
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/* spinlock to protect against concurrent access of EP controller */
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spinlock_t lock;
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};
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#define to_pci_epc(device) container_of((device), struct pci_epc, dev)
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#define pci_epc_create(dev, ops) \
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__pci_epc_create((dev), (ops), THIS_MODULE)
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#define devm_pci_epc_create(dev, ops) \
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__devm_pci_epc_create((dev), (ops), THIS_MODULE)
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static inline void epc_set_drvdata(struct pci_epc *epc, void *data)
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{
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dev_set_drvdata(&epc->dev, data);
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}
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static inline void *epc_get_drvdata(struct pci_epc *epc)
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{
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return dev_get_drvdata(&epc->dev);
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}
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||||
struct pci_epc *
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__devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
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struct module *owner);
|
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struct pci_epc *
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__pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
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struct module *owner);
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void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc);
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void pci_epc_destroy(struct pci_epc *epc);
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int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf);
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void pci_epc_linkup(struct pci_epc *epc);
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void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf);
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int pci_epc_write_header(struct pci_epc *epc, struct pci_epf_header *hdr);
|
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int pci_epc_set_bar(struct pci_epc *epc, enum pci_barno bar,
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dma_addr_t bar_phys, size_t size, int flags);
|
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void pci_epc_clear_bar(struct pci_epc *epc, int bar);
|
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int pci_epc_map_addr(struct pci_epc *epc, phys_addr_t phys_addr,
|
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u64 pci_addr, size_t size);
|
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void pci_epc_unmap_addr(struct pci_epc *epc, phys_addr_t phys_addr);
|
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int pci_epc_set_msi(struct pci_epc *epc, u8 interrupts);
|
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int pci_epc_get_msi(struct pci_epc *epc);
|
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int pci_epc_raise_irq(struct pci_epc *epc, enum pci_epc_irq_type type,
|
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u8 interrupt_num);
|
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int pci_epc_start(struct pci_epc *epc);
|
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void pci_epc_stop(struct pci_epc *epc);
|
||||
struct pci_epc *pci_epc_get(const char *epc_name);
|
||||
void pci_epc_put(struct pci_epc *epc);
|
||||
|
||||
int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_addr, size_t size);
|
||||
void pci_epc_mem_exit(struct pci_epc *epc);
|
||||
void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
|
||||
phys_addr_t *phys_addr, size_t size);
|
||||
void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
|
||||
void __iomem *virt_addr, size_t size);
|
||||
#endif /* __LINUX_PCI_EPC_H */
|
||||
162
include/linux/pci-epf.h
Normal file
162
include/linux/pci-epf.h
Normal file
@@ -0,0 +1,162 @@
|
||||
/**
|
||||
* PCI Endpoint *Function* (EPF) header file
|
||||
*
|
||||
* Copyright (C) 2017 Texas Instruments
|
||||
* Author: Kishon Vijay Abraham I <kishon@ti.com>
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 of
|
||||
* the License as published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_PCI_EPF_H
|
||||
#define __LINUX_PCI_EPF_H
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
|
||||
struct pci_epf;
|
||||
|
||||
enum pci_interrupt_pin {
|
||||
PCI_INTERRUPT_UNKNOWN,
|
||||
PCI_INTERRUPT_INTA,
|
||||
PCI_INTERRUPT_INTB,
|
||||
PCI_INTERRUPT_INTC,
|
||||
PCI_INTERRUPT_INTD,
|
||||
};
|
||||
|
||||
enum pci_barno {
|
||||
BAR_0,
|
||||
BAR_1,
|
||||
BAR_2,
|
||||
BAR_3,
|
||||
BAR_4,
|
||||
BAR_5,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pci_epf_header - represents standard configuration header
|
||||
* @vendorid: identifies device manufacturer
|
||||
* @deviceid: identifies a particular device
|
||||
* @revid: specifies a device-specific revision identifier
|
||||
* @progif_code: identifies a specific register-level programming interface
|
||||
* @subclass_code: identifies more specifically the function of the device
|
||||
* @baseclass_code: broadly classifies the type of function the device performs
|
||||
* @cache_line_size: specifies the system cacheline size in units of DWORDs
|
||||
* @subsys_vendor_id: vendor of the add-in card or subsystem
|
||||
* @subsys_id: id specific to vendor
|
||||
* @interrupt_pin: interrupt pin the device (or device function) uses
|
||||
*/
|
||||
struct pci_epf_header {
|
||||
u16 vendorid;
|
||||
u16 deviceid;
|
||||
u8 revid;
|
||||
u8 progif_code;
|
||||
u8 subclass_code;
|
||||
u8 baseclass_code;
|
||||
u8 cache_line_size;
|
||||
u16 subsys_vendor_id;
|
||||
u16 subsys_id;
|
||||
enum pci_interrupt_pin interrupt_pin;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pci_epf_ops - set of function pointers for performing EPF operations
|
||||
* @bind: ops to perform when a EPC device has been bound to EPF device
|
||||
* @unbind: ops to perform when a binding has been lost between a EPC device
|
||||
* and EPF device
|
||||
* @linkup: ops to perform when the EPC device has established a connection with
|
||||
* a host system
|
||||
*/
|
||||
struct pci_epf_ops {
|
||||
int (*bind)(struct pci_epf *epf);
|
||||
void (*unbind)(struct pci_epf *epf);
|
||||
void (*linkup)(struct pci_epf *epf);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pci_epf_driver - represents the PCI EPF driver
|
||||
* @probe: ops to perform when a new EPF device has been bound to the EPF driver
|
||||
* @remove: ops to perform when the binding between the EPF device and EPF
|
||||
* driver is broken
|
||||
* @driver: PCI EPF driver
|
||||
* @ops: set of function pointers for performing EPF operations
|
||||
* @owner: the owner of the module that registers the PCI EPF driver
|
||||
* @group: configfs group corresponding to the PCI EPF driver
|
||||
* @id_table: identifies EPF devices for probing
|
||||
*/
|
||||
struct pci_epf_driver {
|
||||
int (*probe)(struct pci_epf *epf);
|
||||
int (*remove)(struct pci_epf *epf);
|
||||
|
||||
struct device_driver driver;
|
||||
struct pci_epf_ops *ops;
|
||||
struct module *owner;
|
||||
struct config_group *group;
|
||||
const struct pci_epf_device_id *id_table;
|
||||
};
|
||||
|
||||
#define to_pci_epf_driver(drv) (container_of((drv), struct pci_epf_driver, \
|
||||
driver))
|
||||
|
||||
/**
|
||||
* struct pci_epf_bar - represents the BAR of EPF device
|
||||
* @phys_addr: physical address that should be mapped to the BAR
|
||||
* @size: the size of the address space present in BAR
|
||||
*/
|
||||
struct pci_epf_bar {
|
||||
dma_addr_t phys_addr;
|
||||
size_t size;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pci_epf - represents the PCI EPF device
|
||||
* @dev: the PCI EPF device
|
||||
* @name: the name of the PCI EPF device
|
||||
* @header: represents standard configuration header
|
||||
* @bar: represents the BAR of EPF device
|
||||
* @msi_interrupts: number of MSI interrupts required by this function
|
||||
* @func_no: unique function number within this endpoint device
|
||||
* @epc: the EPC device to which this EPF device is bound
|
||||
* @driver: the EPF driver to which this EPF device is bound
|
||||
* @list: to add pci_epf as a list of PCI endpoint functions to pci_epc
|
||||
*/
|
||||
struct pci_epf {
|
||||
struct device dev;
|
||||
const char *name;
|
||||
struct pci_epf_header *header;
|
||||
struct pci_epf_bar bar[6];
|
||||
u8 msi_interrupts;
|
||||
u8 func_no;
|
||||
|
||||
struct pci_epc *epc;
|
||||
struct pci_epf_driver *driver;
|
||||
struct list_head list;
|
||||
};
|
||||
|
||||
#define to_pci_epf(epf_dev) container_of((epf_dev), struct pci_epf, dev)
|
||||
|
||||
#define pci_epf_register_driver(driver) \
|
||||
__pci_epf_register_driver((driver), THIS_MODULE)
|
||||
|
||||
static inline void epf_set_drvdata(struct pci_epf *epf, void *data)
|
||||
{
|
||||
dev_set_drvdata(&epf->dev, data);
|
||||
}
|
||||
|
||||
static inline void *epf_get_drvdata(struct pci_epf *epf)
|
||||
{
|
||||
return dev_get_drvdata(&epf->dev);
|
||||
}
|
||||
|
||||
struct pci_epf *pci_epf_create(const char *name);
|
||||
void pci_epf_destroy(struct pci_epf *epf);
|
||||
int __pci_epf_register_driver(struct pci_epf_driver *driver,
|
||||
struct module *owner);
|
||||
void pci_epf_unregister_driver(struct pci_epf_driver *driver);
|
||||
void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar);
|
||||
void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar);
|
||||
int pci_epf_bind(struct pci_epf *epf);
|
||||
void pci_epf_unbind(struct pci_epf *epf);
|
||||
void pci_epf_linkup(struct pci_epf *epf);
|
||||
#endif /* __LINUX_PCI_EPF_H */
|
||||
@@ -28,6 +28,7 @@
|
||||
#include <linux/kobject.h>
|
||||
#include <linux/atomic.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/resource_ext.h>
|
||||
#include <uapi/linux/pci.h>
|
||||
@@ -178,6 +179,10 @@ enum pci_dev_flags {
|
||||
PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
|
||||
/* Get VPD from function 0 VPD */
|
||||
PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
|
||||
/* a non-root bridge where translation occurs, stop alias search here */
|
||||
PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
|
||||
/* Do not use FLR even if device advertises PCI_AF_CAP */
|
||||
PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
|
||||
};
|
||||
|
||||
enum pci_irq_reroute_variant {
|
||||
@@ -397,6 +402,8 @@ struct pci_dev {
|
||||
phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
|
||||
size_t romlen; /* Length of ROM if it's not from the BAR */
|
||||
char *driver_override; /* Driver name to force a match */
|
||||
|
||||
unsigned long priv_flags; /* Private flags for the pci driver */
|
||||
};
|
||||
|
||||
static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
|
||||
@@ -941,32 +948,12 @@ int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
|
||||
|
||||
struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
|
||||
|
||||
static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
|
||||
{
|
||||
return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
|
||||
}
|
||||
static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
|
||||
{
|
||||
return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
|
||||
}
|
||||
static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
|
||||
u32 *val)
|
||||
{
|
||||
return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
|
||||
}
|
||||
static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
|
||||
{
|
||||
return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
|
||||
}
|
||||
static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
|
||||
{
|
||||
return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
|
||||
}
|
||||
static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
|
||||
u32 val)
|
||||
{
|
||||
return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
|
||||
}
|
||||
int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
|
||||
int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
|
||||
int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
|
||||
int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
|
||||
int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
|
||||
int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
|
||||
|
||||
int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
|
||||
int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
|
||||
@@ -1053,6 +1040,7 @@ int pcie_get_mps(struct pci_dev *dev);
|
||||
int pcie_set_mps(struct pci_dev *dev, int mps);
|
||||
int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
|
||||
enum pcie_link_width *width);
|
||||
void pcie_flr(struct pci_dev *dev);
|
||||
int __pci_reset_function(struct pci_dev *dev);
|
||||
int __pci_reset_function_locked(struct pci_dev *dev);
|
||||
int pci_reset_function(struct pci_dev *dev);
|
||||
@@ -1073,6 +1061,11 @@ int pci_select_bars(struct pci_dev *dev, unsigned long flags);
|
||||
bool pci_device_is_present(struct pci_dev *pdev);
|
||||
void pci_ignore_hotplug(struct pci_dev *dev);
|
||||
|
||||
int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
|
||||
irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
|
||||
const char *fmt, ...);
|
||||
void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
|
||||
|
||||
/* ROM control related routines */
|
||||
int pci_enable_rom(struct pci_dev *pdev);
|
||||
void pci_disable_rom(struct pci_dev *pdev);
|
||||
@@ -1200,6 +1193,11 @@ unsigned long pci_address_to_pio(phys_addr_t addr);
|
||||
phys_addr_t pci_pio_to_address(unsigned long pio);
|
||||
int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
|
||||
void pci_unmap_iospace(struct resource *res);
|
||||
void __iomem *devm_pci_remap_cfgspace(struct device *dev,
|
||||
resource_size_t offset,
|
||||
resource_size_t size);
|
||||
void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
|
||||
struct resource *res);
|
||||
|
||||
static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
|
||||
{
|
||||
@@ -1298,10 +1296,8 @@ struct msix_entry {
|
||||
|
||||
#ifdef CONFIG_PCI_MSI
|
||||
int pci_msi_vec_count(struct pci_dev *dev);
|
||||
void pci_msi_shutdown(struct pci_dev *dev);
|
||||
void pci_disable_msi(struct pci_dev *dev);
|
||||
int pci_msix_vec_count(struct pci_dev *dev);
|
||||
void pci_msix_shutdown(struct pci_dev *dev);
|
||||
void pci_disable_msix(struct pci_dev *dev);
|
||||
void pci_restore_msi_state(struct pci_dev *dev);
|
||||
int pci_msi_enabled(void);
|
||||
@@ -1327,10 +1323,8 @@ int pci_irq_get_node(struct pci_dev *pdev, int vec);
|
||||
|
||||
#else
|
||||
static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
|
||||
static inline void pci_msi_shutdown(struct pci_dev *dev) { }
|
||||
static inline void pci_disable_msi(struct pci_dev *dev) { }
|
||||
static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
|
||||
static inline void pci_msix_shutdown(struct pci_dev *dev) { }
|
||||
static inline void pci_disable_msix(struct pci_dev *dev) { }
|
||||
static inline void pci_restore_msi_state(struct pci_dev *dev) { }
|
||||
static inline int pci_msi_enabled(void) { return 0; }
|
||||
@@ -1623,6 +1617,36 @@ static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
|
||||
|
||||
#include <asm/pci.h>
|
||||
|
||||
/* These two functions provide almost identical functionality. Depennding
|
||||
* on the architecture, one will be implemented as a wrapper around the
|
||||
* other (in drivers/pci/mmap.c).
|
||||
*
|
||||
* pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
|
||||
* is expected to be an offset within that region.
|
||||
*
|
||||
* pci_mmap_page_range() is the legacy architecture-specific interface,
|
||||
* which accepts a "user visible" resource address converted by
|
||||
* pci_resource_to_user(), as used in the legacy mmap() interface in
|
||||
* /proc/bus/pci/.
|
||||
*/
|
||||
int pci_mmap_resource_range(struct pci_dev *dev, int bar,
|
||||
struct vm_area_struct *vma,
|
||||
enum pci_mmap_state mmap_state, int write_combine);
|
||||
int pci_mmap_page_range(struct pci_dev *pdev, int bar,
|
||||
struct vm_area_struct *vma,
|
||||
enum pci_mmap_state mmap_state, int write_combine);
|
||||
|
||||
#ifndef arch_can_pci_mmap_wc
|
||||
#define arch_can_pci_mmap_wc() 0
|
||||
#endif
|
||||
|
||||
#ifndef arch_can_pci_mmap_io
|
||||
#define arch_can_pci_mmap_io() 0
|
||||
#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
|
||||
#else
|
||||
int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
|
||||
#endif
|
||||
|
||||
#ifndef pci_root_bus_fwnode
|
||||
#define pci_root_bus_fwnode(bus) NULL
|
||||
#endif
|
||||
|
||||
@@ -862,6 +862,8 @@
|
||||
#define PCI_DEVICE_ID_TI_X620 0xac8d
|
||||
#define PCI_DEVICE_ID_TI_X420 0xac8e
|
||||
#define PCI_DEVICE_ID_TI_XX20_FM 0xac8f
|
||||
#define PCI_DEVICE_ID_TI_DRA74x 0xb500
|
||||
#define PCI_DEVICE_ID_TI_DRA72x 0xb501
|
||||
|
||||
#define PCI_VENDOR_ID_SONY 0x104d
|
||||
|
||||
|
||||
Reference in New Issue
Block a user