Merge branch 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 platform updates from Ingo Molnar: "The main changes in this cycle are: - Intel SOC driver updates, by Aubrey Li. - TS5500 platform updates, by Vivien Didelot" * 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/pmc_atom: Silence shift wrapping warnings in pmc_sleep_tmr_show() x86/pmc_atom: Expose PMC device state and platform sleep state x86/pmc_atom: Eisable a few S0ix wake up events for S0ix residency x86/platform: New Intel Atom SOC power management controller driver x86/platform/ts5500: Add support for TS-5400 boards x86/platform/ts5500: Add a 'name' sysfs attribute x86/platform/ts5500: Use the DEVICE_ATTR_RO() macro
This commit is contained in:
Linus Torvalds
@@ -106,6 +106,7 @@ obj-$(CONFIG_EFI) += sysfb_efi.o
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obj-$(CONFIG_PERF_EVENTS) += perf_regs.o
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obj-$(CONFIG_TRACING) += tracepoint.o
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obj-$(CONFIG_IOSF_MBI) += iosf_mbi.o
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obj-$(CONFIG_PMC_ATOM) += pmc_atom.o
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###
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# 64 bit specific files
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321
arch/x86/kernel/pmc_atom.c
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321
arch/x86/kernel/pmc_atom.c
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@@ -0,0 +1,321 @@
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/*
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* Intel Atom SOC Power Management Controller Driver
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* Copyright (c) 2014, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/device.h>
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#include <linux/io.h>
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#include <asm/pmc_atom.h>
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#define DRIVER_NAME KBUILD_MODNAME
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struct pmc_dev {
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u32 base_addr;
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void __iomem *regmap;
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#ifdef CONFIG_DEBUG_FS
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struct dentry *dbgfs_dir;
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#endif /* CONFIG_DEBUG_FS */
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};
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static struct pmc_dev pmc_device;
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static u32 acpi_base_addr;
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struct pmc_dev_map {
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const char *name;
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u32 bit_mask;
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};
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static const struct pmc_dev_map dev_map[] = {
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{"0 - LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
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{"1 - LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
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{"2 - LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2},
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{"3 - LPSS1_F3_HSUART1", BIT_LPSS1_F3_HSUART1},
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{"4 - LPSS1_F4_HSUART2", BIT_LPSS1_F4_HSUART2},
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{"5 - LPSS1_F5_SPI", BIT_LPSS1_F5_SPI},
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{"6 - LPSS1_F6_Reserved", BIT_LPSS1_F6_XXX},
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{"7 - LPSS1_F7_Reserved", BIT_LPSS1_F7_XXX},
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{"8 - SCC_EMMC", BIT_SCC_EMMC},
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{"9 - SCC_SDIO", BIT_SCC_SDIO},
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{"10 - SCC_SDCARD", BIT_SCC_SDCARD},
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{"11 - SCC_MIPI", BIT_SCC_MIPI},
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{"12 - HDA", BIT_HDA},
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{"13 - LPE", BIT_LPE},
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{"14 - OTG", BIT_OTG},
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{"15 - USH", BIT_USH},
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{"16 - GBE", BIT_GBE},
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{"17 - SATA", BIT_SATA},
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{"18 - USB_EHCI", BIT_USB_EHCI},
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{"19 - SEC", BIT_SEC},
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{"20 - PCIE_PORT0", BIT_PCIE_PORT0},
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{"21 - PCIE_PORT1", BIT_PCIE_PORT1},
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{"22 - PCIE_PORT2", BIT_PCIE_PORT2},
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{"23 - PCIE_PORT3", BIT_PCIE_PORT3},
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{"24 - LPSS2_F0_DMA", BIT_LPSS2_F0_DMA},
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{"25 - LPSS2_F1_I2C1", BIT_LPSS2_F1_I2C1},
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{"26 - LPSS2_F2_I2C2", BIT_LPSS2_F2_I2C2},
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{"27 - LPSS2_F3_I2C3", BIT_LPSS2_F3_I2C3},
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{"28 - LPSS2_F3_I2C4", BIT_LPSS2_F4_I2C4},
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{"29 - LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5},
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{"30 - LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6},
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{"31 - LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7},
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{"32 - SMB", BIT_SMB},
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{"33 - OTG_SS_PHY", BIT_OTG_SS_PHY},
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{"34 - USH_SS_PHY", BIT_USH_SS_PHY},
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{"35 - DFX", BIT_DFX},
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};
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static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
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{
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return readl(pmc->regmap + reg_offset);
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}
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static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val)
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{
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writel(val, pmc->regmap + reg_offset);
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}
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static void pmc_power_off(void)
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{
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u16 pm1_cnt_port;
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u32 pm1_cnt_value;
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pr_info("Preparing to enter system sleep state S5\n");
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pm1_cnt_port = acpi_base_addr + PM1_CNT;
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pm1_cnt_value = inl(pm1_cnt_port);
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pm1_cnt_value &= SLEEP_TYPE_MASK;
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pm1_cnt_value |= SLEEP_TYPE_S5;
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pm1_cnt_value |= SLEEP_ENABLE;
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outl(pm1_cnt_value, pm1_cnt_port);
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}
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static void pmc_hw_reg_setup(struct pmc_dev *pmc)
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{
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/*
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* Disable PMC S0IX_WAKE_EN events coming from:
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* - LPC clock run
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* - GPIO_SUS ored dedicated IRQs
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* - GPIO_SCORE ored dedicated IRQs
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* - GPIO_SUS shared IRQ
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* - GPIO_SCORE shared IRQ
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*/
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pmc_reg_write(pmc, PMC_S0IX_WAKE_EN, (u32)PMC_WAKE_EN_SETTING);
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}
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#ifdef CONFIG_DEBUG_FS
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static int pmc_dev_state_show(struct seq_file *s, void *unused)
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{
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struct pmc_dev *pmc = s->private;
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u32 func_dis, func_dis_2, func_dis_index;
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u32 d3_sts_0, d3_sts_1, d3_sts_index;
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int dev_num, dev_index, reg_index;
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func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
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func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
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d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
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d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
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dev_num = ARRAY_SIZE(dev_map);
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for (dev_index = 0; dev_index < dev_num; dev_index++) {
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reg_index = dev_index / PMC_REG_BIT_WIDTH;
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if (reg_index) {
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func_dis_index = func_dis_2;
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d3_sts_index = d3_sts_1;
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} else {
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func_dis_index = func_dis;
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d3_sts_index = d3_sts_0;
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}
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seq_printf(s, "Dev: %-32s\tState: %s [%s]\n",
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dev_map[dev_index].name,
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dev_map[dev_index].bit_mask & func_dis_index ?
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"Disabled" : "Enabled ",
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dev_map[dev_index].bit_mask & d3_sts_index ?
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"D3" : "D0");
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}
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return 0;
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}
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static int pmc_dev_state_open(struct inode *inode, struct file *file)
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{
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return single_open(file, pmc_dev_state_show, inode->i_private);
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}
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static const struct file_operations pmc_dev_state_ops = {
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.open = pmc_dev_state_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static int pmc_sleep_tmr_show(struct seq_file *s, void *unused)
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{
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struct pmc_dev *pmc = s->private;
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u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;
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s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
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s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
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s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
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s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
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s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
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seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
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seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);
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seq_printf(s, "S0I2 Residency:\t%lldus\n", s0i2_tmr);
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seq_printf(s, "S0I3 Residency:\t%lldus\n", s0i3_tmr);
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seq_printf(s, "S0 Residency:\t%lldus\n", s0_tmr);
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return 0;
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}
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static int pmc_sleep_tmr_open(struct inode *inode, struct file *file)
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{
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return single_open(file, pmc_sleep_tmr_show, inode->i_private);
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}
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static const struct file_operations pmc_sleep_tmr_ops = {
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.open = pmc_sleep_tmr_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static void pmc_dbgfs_unregister(struct pmc_dev *pmc)
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{
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if (!pmc->dbgfs_dir)
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return;
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debugfs_remove_recursive(pmc->dbgfs_dir);
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pmc->dbgfs_dir = NULL;
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}
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static int pmc_dbgfs_register(struct pmc_dev *pmc, struct pci_dev *pdev)
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{
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struct dentry *dir, *f;
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dir = debugfs_create_dir("pmc_atom", NULL);
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if (!dir)
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return -ENOMEM;
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f = debugfs_create_file("dev_state", S_IFREG | S_IRUGO,
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dir, pmc, &pmc_dev_state_ops);
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if (!f) {
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dev_err(&pdev->dev, "dev_states register failed\n");
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goto err;
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}
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f = debugfs_create_file("sleep_state", S_IFREG | S_IRUGO,
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dir, pmc, &pmc_sleep_tmr_ops);
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if (!f) {
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dev_err(&pdev->dev, "sleep_state register failed\n");
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goto err;
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}
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pmc->dbgfs_dir = dir;
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return 0;
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err:
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pmc_dbgfs_unregister(pmc);
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return -ENODEV;
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}
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#endif /* CONFIG_DEBUG_FS */
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static int pmc_setup_dev(struct pci_dev *pdev)
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{
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struct pmc_dev *pmc = &pmc_device;
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int ret;
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/* Obtain ACPI base address */
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pci_read_config_dword(pdev, ACPI_BASE_ADDR_OFFSET, &acpi_base_addr);
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acpi_base_addr &= ACPI_BASE_ADDR_MASK;
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/* Install power off function */
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if (acpi_base_addr != 0 && pm_power_off == NULL)
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pm_power_off = pmc_power_off;
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pci_read_config_dword(pdev, PMC_BASE_ADDR_OFFSET, &pmc->base_addr);
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pmc->base_addr &= PMC_BASE_ADDR_MASK;
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pmc->regmap = ioremap_nocache(pmc->base_addr, PMC_MMIO_REG_LEN);
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if (!pmc->regmap) {
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dev_err(&pdev->dev, "error: ioremap failed\n");
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return -ENOMEM;
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}
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/* PMC hardware registers setup */
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pmc_hw_reg_setup(pmc);
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#ifdef CONFIG_DEBUG_FS
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ret = pmc_dbgfs_register(pmc, pdev);
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if (ret) {
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iounmap(pmc->regmap);
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return ret;
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}
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#endif /* CONFIG_DEBUG_FS */
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return 0;
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}
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/*
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* Data for PCI driver interface
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*
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* This data only exists for exporting the supported
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* PCI ids via MODULE_DEVICE_TABLE. We do not actually
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* register a pci_driver, because lpc_ich will register
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* a driver on the same PCI id.
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*/
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static const struct pci_device_id pmc_pci_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_VLV_PMC) },
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, pmc_pci_ids);
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static int __init pmc_atom_init(void)
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{
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int err = -ENODEV;
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struct pci_dev *pdev = NULL;
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const struct pci_device_id *ent;
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/* We look for our device - PCU PMC
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* we assume that there is max. one device.
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*
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* We can't use plain pci_driver mechanism,
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* as the device is really a multiple function device,
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* main driver that binds to the pci_device is lpc_ich
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* and have to find & bind to the device this way.
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*/
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for_each_pci_dev(pdev) {
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ent = pci_match_id(pmc_pci_ids, pdev);
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if (ent) {
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err = pmc_setup_dev(pdev);
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goto out;
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}
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}
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/* Device not found. */
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out:
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return err;
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}
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module_init(pmc_atom_init);
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/* no module_exit, this driver shouldn't be unloaded */
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MODULE_AUTHOR("Aubrey Li <aubrey.li@linux.intel.com>");
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MODULE_DESCRIPTION("Intel Atom SOC Power Management Controller Interface");
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MODULE_LICENSE("GPL v2");
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Block a user